- Jun 10, 2014
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Mario Kleiner authored
Cards with nv04 display engine can't reliably use vblank counts and timestamps computed via drm_handle_vblank(), as the function gets invoked after sending the pageflip events. Fix this by defaulting to the old crtcid = -1 fallback path on <= NV-50 cards, and only using the precise path on NV-50 and later. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.13+
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Mario Kleiner authored
Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was responsible for calling both, the vblank-irq handler (display engine irq) and kms-pageflip completion handler (from fifo irq), the order of invocation was wrong. nouveau_finish_flip() was called before drm_handle_vblank() for the vblank of pageflip completion, so the emitted pageflip event contained stale vblank count and timestamp from previous vblank. This caused failure in userspace to timestamp properly. Reorder order of invocation of engine irq handlers: Put NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO, so that drm_handle_vblank() gets called to update vblank timestamps and count before potential pageflip events make use of that information. This works on nv-50 and later, where kms-pageflip completion triggers an irq either after a separate vblank irq, or both pageflip and vblank trigger one common irq invocation, but never before vblank irqs. v2 (Ben): - removed mods for nv04-nv40, it doesn't help there anyway - this is considered a hack, and a better solution should be found Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.13+
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Mario Kleiner authored
nv04_disp_scanoutpos() must abort to trigger simple timestamping fallback if vtotal/htotal regs return zero. This happens if the output isn't a digital output, but a vga analog output, as the regs don't get initialized in that case. Fixes timestamping failure on nv-40 and earlier with vga output. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Cc: <stable@vger.kernel.org> # 3.14+
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
Leave debug for the more interesting bits of info. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ilia Mirkin authored
Use with caution. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ilia Mirkin authored
Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Martin Peres authored
Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Martin Peres authored
Some adt7473 can't manage the 20µs delay we use for the bitbanging, bumping it to 40µs seem to do the trick. Signed-off-by:
Martin Peres <martin.peres@free.fr> Tested-by:
Marcel Dopita <mdop@seznam.cz>
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Martin Peres authored
I spent some time this weekend trying to find in the vbios the number of pulses per revolutions in the vbios but couldn't find it. It would seem all my cards have 2 pulses per revolution so let's stick to that until further notice. Thermal table's id 0x48 may indicate this information but it would seem that changing the value results in the blob power or clock gating the RPM counter... We should ask NVIDIA about that, should be trivial-enough for them to answer. Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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John Rowley authored
Only tested on nvf1, was advised to enable on all. Signed-off-by:
John Rowley <john.rowley08@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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John Rowley authored
Signed-off-by:
John Rowley <john.rowley08@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Set the correct subdev/engine classes when GK20A (0xea) is probed. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Add a GR device for GK20A based on NVE4, with the correct classes definitions (GK20A's 3D class is 0xa297). Most of the NVE4 code can be used on GK20A, so make relevant bits of NVE4 available to other chips as well. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Pad the microcode to a multiple of 0x40 words, otherwise firmware will fail to run from non-prepadded firmware files. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
nvc0_graph_ctor() would only let the graphics engine be enabled if its oclass has a proper microcode linked to it. This prevents GR from being enabled at all on chips that rely exclusively on external firmware, even though such a use-case is valid. Relax the conditions enabling the GR engine to also include the case where an external firmware has also been loaded. Also switch to external firmware if the graph class has no microcode linked to it. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
GK20A's FIFO is compatible with NVE0, but only features 128 channels and 1 runlist. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Add a simple FB device for GK20A, as well as a RAM implementation suitable for chips that use system memory as video RAM. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Add support for initializing the priv ring of GK20A. This is done by the BIOS on desktop GPUs, but needs to be done by hand on Tegra. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Adapt the NVC0 BAR driver to make it able to support chips that do not expose a BAR3. When this happens, BAR1 is then used for USERD mapping and the BAR alloc() functions is disabled, making GPU objects unable to rely on BAR for data access and falling back to PRAMIN. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Some chips that use system memory exclusively (e.g. GK20A) do not expose 2 BAR regions. For them only BAR1 exists, and it should be used for USERD mapping. Do not map BAR3 if its resource does not exist. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Damien Lespiau authored
Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/panel: Changes for v3.16-rc1 This set of commits contains a couple of fixes to existing panel drivers and support for some new panels. One commit touches the DRM core in that in modifies the MIPI DSI support to hook up the shutdown function so that drivers can provide code that's run on shutdown. This is used by a subsequent commit to make the simple panel driver power off the backlight on shutdown. * tag 'drm/panel/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/panel: simple - Add AUO B133XTN01 panel support drm/panel: simple - Disable panel on shutdown drm/panel: add support for EDT ET057090DHU panel drm/panel: Add support for EDT ETM0700G0DH6 and ET070080DH6 panels drm/panel: ld9040: add power control sequence drm/panel: s6e8aa0: silence array overflow warning drm/dsi: Support device shutdown
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git://anongit.freedesktop.org/tegra/linuxDave Airlie authored
drm/tegra: Changes for v3.16-rc1 The majority of these changes are a slew of cleanups across the board. A more noteworthy change is the addition of drm_dev_set_unique() and the conversion of the Tegra DRM driver to use it. This allows us to get rid of the host1x drm_bus implementation. Other USB and platform drivers can be changed in a similar way. Unfortunately for most PCI devices there is some userspace that relies on the old functionality and cannot be as easily converted. HDMI and hardware cursor support is added for Tegra124. The SOR output gains support for exposing CRCs via debugfs, which can be used for automated testing. Many values that were hardcoded in the SOR/eDP code are now computed at runtime to increase compatibility with more devices. * tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: (47 commits) drm/tegra: sor - Remove obsolete comment drm/tegra: sor - Enable only the necessary number of lanes drm/tegra: sor - Power on only the necessary lanes drm/tegra: sor - Do not program interlaced mode registers drm/tegra: sor - Do not hardcode link speed drm/tegra: sor - Do not hardcode number of blank symbols drm/tegra: sor - Don't hardcode link parameters drm/tegra: sor - Change power down ordering drm/tegra: sor - Fix copy/paste error drm/tegra: sor - Remove pixel clock rounding drm/tegra: sor - Make debugfs setup consistent drm/tegra: sor - Recursively remove debugfs tree drm/tegra: dp - Mark the connector as hotplug capable drm/tegra: dp - Implement hotplug detection in work queue drm/tegra: Add hardware cursor support drm/tegra: Remove host1x drm_bus implementation drm: Document how to register devices without struct drm_bus drm: Add device registration documentation drm: Introduce drm_dev_set_unique() gpu: host1x: Rename internal functions for clarity ...
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- Jun 09, 2014
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Stéphane Marchesin authored
This panel is used by nyan-big and can be supported by the simple-panel driver. Signed-off-by:
Stéphane Marchesin <marcheu@chromium.org> [treding@nvidia.com: add device tree binding document] Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
According to the DP specification the disparity of the first symbol should always be negative. It is therefore safe to assume that panels will conform to that and therefore parameterizing this field should never be necessary. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Power on only those lanes required for the specified link. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Interlaced mode is currently not supported on the SOR, so don't program any associated registers. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The number of HBLANK and VBLANK symbols can be computed at runtime so that they can be set appropriately depending on the video mode and DP link. These values are used by the packet generation logic to determine how many audio samples can be transferred during the blanking intervals. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The currently hardcoded link parameters don't work on all eDP panels, so compute the parameters at runtime depending on the mode and panel type to allow the driver to cope with a wider variety of panels. Note that the number of bits per pixel of the panel is still hardcoded, but this can be addressed in a separate patch. This is largely based on a patch by Stéphane Marchesin but the algorithm was largely rewritten to be more readable and concise. Signed-off-by:
Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Stéphane Marchesin authored
Lanes are powered up in decreasing order. Power them down in increasing order for consistency. Signed-off-by:
Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Stéphane Marchesin authored
The comment above mentions link A/B but this isn't what the code does, so let's fix that. Signed-off-by:
Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Stéphane Marchesin authored
The code currently rounds up the clock to the next MHZ, which is rounding up a 69.5MHz clock to 70MHz on my machine. This in turn prevents the display from syncing. Removing this rounding fixes eDP for me. Signed-off-by:
Stéphane Marchesin <marcheu@chromium.org> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Jun 06, 2014
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
> Bunch of stuff for 3.16 still: > - Mipi dsi panel support for byt. Finally! From Shobhit&others. I've > squeezed this in since it's a regression compared to vbios and we've > been ridiculed about it a bit too often ... > - connection_mutex deadlock fix in get_connector (only affects i915). > - Core patches from Matt's primary plane from Matt Roper, I've pushed the > i915 stuff to 3.17. > - vlv power well sequencing fixes from Jesse. > - Fix for cursor size changes from Chris. > - agpbusy fixes from Ville. > - A few smaller things. > * tag 'drm-intel-fixes-2014-06-06' of git://anongit.freedesktop.org/drm-intel: (32 commits) drm/i915: BDW: Adding missing cursor offsets. drm: Fix getconnector connection_mutex locking drm/i915/bdw: Only use 2g GGTT for 32b platforms drm/i915: Nuke pipe A quirk on i830M drm/i915: fix display power sw state reporting drm/i915: Always apply cursor width changes drm/i915: tell the user if both KMS and UMS are disabled drm/plane-helper: Add drm_plane_helper_check_update() (v3) drm: Check CRTC compatibility in setplane drm/i915: use VBT to determine whether to enumerate the VGA port drm/i915: Don't WARN about ring idle bit on gen2 drm/i915: Silence the WARN if the user tries to GTT mmap an incoherent object drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS drm/i915: Enable interrupt-based AGPBUSY# enable on 85x drm/i915: Flip the sense of AGPBUSY_DIS bit drm/i915: Set AGPBUSY# bit in init_clock_gating drm/i915/vlv: add pll assertion when disabling DPIO common well drm/i915/vlv: move DPIO common reset de-assert into __vlv_set_power_well drm/i915/vlv: re-order power wells so DPIO common comes after TX drm/i915/vlv: move CRI refclk enable into __vlv_set_power_well ...
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Thierry Reding authored
Other output drivers set up debugfs slightly differently. Bring the SOR driver in line with those for consistency. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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