Commit 6e8e268b authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/disp/dp: support training pattern 3 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent fb7c2a71

drivers/gpu/drm/nouveau/core/engine/disp/dport.c

+7 −2
Original line number Diff line number Diff line
@@ -202,6 +202,9 @@ dp_link_train_eq(struct dp_state *dp) 
	bool eq_done = false, cr_done = true;

	int tries = 0, i;



	if (dp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED)

		dp_set_training_pattern(dp, 3);

	else

		dp_set_training_pattern(dp, 2);



	do {
@@ -316,8 +319,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func, 
	}



	/* bring capabilities within encoder limits */

	if (nv_oclass(disp)->handle < NV_ENGINE(DISP, 0x90))

		dp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;

	if ((dp->dpcd[2] & 0x1f) > dp->outp->dpconf.link_nr) {

		dp->dpcd[2] &= ~0x1f;

		dp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;

		dp->dpcd[2] |= dp->outp->dpconf.link_nr;

	}

	if (dp->dpcd[1] > dp->outp->dpconf.link_bw)

drivers/gpu/drm/nouveau/core/engine/disp/dport.h

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#define DPCD_RC01_MAX_LINK_RATE                                         0x00001

#define DPCD_RC02                                                       0x00002

#define DPCD_RC02_ENHANCED_FRAME_CAP                                       0x80

#define DPCD_RC02_TPS3_SUPPORTED                                           0x40

#define DPCD_RC02_MAX_LANE_COUNT                                           0x1f

#define DPCD_RC03                                                       0x00003

#define DPCD_RC03_MAX_DOWNSPREAD                                           0x01