rk3399.dtsi

			/* These power domains are grouped by VD_CENTER */
			pd_iep@RK3399_PD_IEP {
				reg = <RK3399_PD_IEP>;
				clocks = <&cru ACLK_IEP>,
					 <&cru HCLK_IEP>;
				pm_qos = <&qos_iep>;
			};
			pd_rga@RK3399_PD_RGA {
				reg = <RK3399_PD_RGA>;
				clocks = <&cru ACLK_RGA>,
					 <&cru HCLK_RGA>;
				pm_qos = <&qos_rga_r>,
					 <&qos_rga_w>;
			};
			pd_vcodec@RK3399_PD_VCODEC {
				reg = <RK3399_PD_VCODEC>;
				clocks = <&cru ACLK_VCODEC>,
					 <&cru HCLK_VCODEC>;
				pm_qos = <&qos_video_m0>;
			};
			pd_vdu@RK3399_PD_VDU {
				reg = <RK3399_PD_VDU>;
				clocks = <&cru ACLK_VDU>,
					 <&cru HCLK_VDU>;
				pm_qos = <&qos_video_m1_r>,
					 <&qos_video_m1_w>;
			};

			/* These power domains are grouped by VD_GPU */
			pd_gpu@RK3399_PD_GPU {
				reg = <RK3399_PD_GPU>;
				clocks = <&cru ACLK_GPU>;
				pm_qos = <&qos_gpu>;
			};

			/* These power domains are grouped by VD_LOGIC */
			pd_edp@RK3399_PD_EDP {
				reg = <RK3399_PD_EDP>;
				clocks = <&cru PCLK_EDP_CTRL>;
			};
			pd_emmc@RK3399_PD_EMMC {
				reg = <RK3399_PD_EMMC>;
				clocks = <&cru ACLK_EMMC>;
				pm_qos = <&qos_emmc>;
			};
			pd_gmac@RK3399_PD_GMAC {
				reg = <RK3399_PD_GMAC>;
				clocks = <&cru ACLK_GMAC>,
					 <&cru PCLK_GMAC>;
				pm_qos = <&qos_gmac>;
			};
			pd_sd@RK3399_PD_SD {
				reg = <RK3399_PD_SD>;
				clocks = <&cru HCLK_SDMMC>,
					 <&cru SCLK_SDMMC>;
				pm_qos = <&qos_sd>;
			};
			pd_sdioaudio@RK3399_PD_SDIOAUDIO {
				reg = <RK3399_PD_SDIOAUDIO>;
				clocks = <&cru HCLK_SDIO>;
				pm_qos = <&qos_sdioaudio>;
			};
			pd_tcpc0@RK3399_PD_TCPD0 {
				reg = <RK3399_PD_TCPD0>;
				clocks = <&cru SCLK_UPHY0_TCPDCORE>,
					 <&cru SCLK_UPHY0_TCPDPHY_REF>;
			};
			pd_tcpc1@RK3399_PD_TCPD1 {
				reg = <RK3399_PD_TCPD1>;
				clocks = <&cru SCLK_UPHY1_TCPDCORE>,
					 <&cru SCLK_UPHY1_TCPDPHY_REF>;
			};
			pd_usb3@RK3399_PD_USB3 {
				reg = <RK3399_PD_USB3>;
				clocks = <&cru ACLK_USB3>;
				pm_qos = <&qos_usb_otg0>,
					 <&qos_usb_otg1>;
			};
			pd_vio@RK3399_PD_VIO {
				reg = <RK3399_PD_VIO>;
				#address-cells = <1>;
				#size-cells = <0>;

				pd_hdcp@RK3399_PD_HDCP {
					reg = <RK3399_PD_HDCP>;
					clocks = <&cru ACLK_HDCP>,
						 <&cru HCLK_HDCP>,
						 <&cru PCLK_HDCP>;
					pm_qos = <&qos_hdcp>;
				};
				pd_isp0@RK3399_PD_ISP0 {
					reg = <RK3399_PD_ISP0>;
					clocks = <&cru ACLK_ISP0>,
						 <&cru HCLK_ISP0>;
					pm_qos = <&qos_isp0_m0>,
						 <&qos_isp0_m1>;
				};
				pd_isp1@RK3399_PD_ISP1 {
					reg = <RK3399_PD_ISP1>;
					clocks = <&cru ACLK_ISP1>,
						 <&cru HCLK_ISP1>;
					pm_qos = <&qos_isp1_m0>,
						 <&qos_isp1_m1>;
				};
				pd_vo@RK3399_PD_VO {
					reg = <RK3399_PD_VO>;
					#address-cells = <1>;
					#size-cells = <0>;

					pd_vopb@RK3399_PD_VOPB {
						reg = <RK3399_PD_VOPB>;
						clocks = <&cru ACLK_VOP0>,
							 <&cru HCLK_VOP0>;
						pm_qos = <&qos_vop_big_r>,
							 <&qos_vop_big_w>;
					};
					pd_vopl@RK3399_PD_VOPL {
						reg = <RK3399_PD_VOPL>;
						clocks = <&cru ACLK_VOP1>,
							 <&cru HCLK_VOP1>;
						pm_qos = <&qos_vop_little>;
					};
				};
			};
		};
	};

	pmugrf: syscon@ff320000 {
		compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xff320000 0x0 0x1000>;

		pmu_io_domains: io-domains {
			compatible = "rockchip,rk3399-pmu-io-voltage-domain";
			status = "disabled";
		};
	};

	spi3: spi@ff350000 {
		compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff350000 0x0 0x1000>;
		clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
		clock-names = "spiclk", "apb_pclk";
		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	uart4: serial@ff370000 {
		compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff370000 0x0 0x100>;
		clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
		clock-names = "baudclk", "apb_pclk";
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
		reg-shift = <2>;
		reg-io-width = <4>;
		pinctrl-names = "default";
		pinctrl-0 = <&uart4_xfer>;
		status = "disabled";
	};

	i2c0: i2c@ff3c0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff3c0000 0x0 0x1000>;
		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
		assigned-clock-rates = <200000000>;
		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c4: i2c@ff3d0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff3d0000 0x0 0x1000>;
		assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
		assigned-clock-rates = <200000000>;
		clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c8: i2c@ff3e0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff3e0000 0x0 0x1000>;
		assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
		assigned-clock-rates = <200000000>;
		clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
		clock-names = "i2c", "pclk";
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c8_xfer>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pwm0: pwm@ff420000 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420000 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm1: pwm@ff420010 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420010 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm2: pwm@ff420020 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420020 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		clock-names = "pwm";
		status = "disabled";
	};

	pwm3: pwm@ff420030 {
		compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
		reg = <0x0 0xff420030 0x0 0x10>;
		#pwm-cells = <3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3a_pin>;
		clocks = <&pmucru PCLK_RKPWM_PMU>;
		clock-names = "pwm";
		status = "disabled";
	};

	vpu: video-codec@ff650000 {
		compatible = "rockchip,rk3399-vpu";
		reg = <0x0 0xff650000 0x0 0x800>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vepu", "vdpu";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "hclk";
		iommus = <&vpu_mmu>;
		power-domains = <&power RK3399_PD_VCODEC>;
	};

	vpu_mmu: iommu@ff650800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff650800 0x0 0x40>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vpu_mmu";
		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3399_PD_VCODEC>;
	};

	vdec: video-codec@ff660000 {
		compatible = "rockchip,rk3399-vdec";
		reg = <0x0 0xff660000 0x0 0x400>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
			 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
		clock-names = "axi", "ahb", "cabac", "core";
		iommus = <&vdec_mmu>;
		power-domains = <&power RK3399_PD_VDU>;
	};

	vdec_mmu: iommu@ff660480 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vdec_mmu";
		clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3399_PD_VDU>;
		#iommu-cells = <0>;
	};

	iep_mmu: iommu@ff670800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff670800 0x0 0x40>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "iep_mmu";
		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		status = "disabled";
	};

	rga: rga@ff680000 {
		compatible = "rockchip,rk3399-rga";
		reg = <0x0 0xff680000 0x0 0x10000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
		clock-names = "aclk", "hclk", "sclk";
		resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
		reset-names = "core", "axi", "ahb";
		power-domains = <&power RK3399_PD_RGA>;
	};

	efuse0: efuse@ff690000 {
		compatible = "rockchip,rk3399-efuse";
		reg = <0x0 0xff690000 0x0 0x80>;
		#address-cells = <1>;
		#size-cells = <1>;
		clocks = <&cru PCLK_EFUSE1024NS>;
		clock-names = "pclk_efuse";

		/* Data cells */
		cpu_id: cpu-id@7 {
			reg = <0x07 0x10>;
		};
		cpub_leakage: cpu-leakage@17 {
			reg = <0x17 0x1>;
		};
		gpu_leakage: gpu-leakage@18 {
			reg = <0x18 0x1>;
		};
		center_leakage: center-leakage@19 {
			reg = <0x19 0x1>;
		};
		cpul_leakage: cpu-leakage@1a {
			reg = <0x1a 0x1>;
		};
		logic_leakage: logic-leakage@1b {
			reg = <0x1b 0x1>;
		};
		wafer_info: wafer-info@1c {
			reg = <0x1c 0x1>;
		};
	};

	pmucru: pmu-clock-controller@ff750000 {
		compatible = "rockchip,rk3399-pmucru";
		reg = <0x0 0xff750000 0x0 0x1000>;
		rockchip,grf = <&pmugrf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&pmucru PLL_PPLL>;
		assigned-clock-rates = <676000000>;
	};

	cru: clock-controller@ff760000 {
		compatible = "rockchip,rk3399-cru";
		reg = <0x0 0xff760000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks =
			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
			<&cru PLL_NPLL>,
			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
			<&cru PCLK_PERIHP>,
			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
			<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
			<&cru ACLK_GIC_PRE>,
			<&cru PCLK_DDR>;
		assigned-clock-rates =
			 <594000000>,  <800000000>,
			<1000000000>,
			 <150000000>,   <75000000>,
			  <37500000>,
			 <100000000>,  <100000000>,
			  <50000000>, <600000000>,
			 <100000000>,   <50000000>,
			 <400000000>, <400000000>,
			 <200000000>,
			 <200000000>;
	};

	grf: syscon@ff770000 {
		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
		reg = <0x0 0xff770000 0x0 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;

		io_domains: io-domains {
			compatible = "rockchip,rk3399-io-voltage-domain";
			status = "disabled";
		};

		mipi_dphy_rx0: mipi-dphy-rx0 {
			compatible = "rockchip,rk3399-mipi-dphy-rx0";
			clocks = <&cru SCLK_MIPIDPHY_REF>,
				 <&cru SCLK_DPHY_RX0_CFG>,
				 <&cru PCLK_VIO_GRF>;
			clock-names = "dphy-ref", "dphy-cfg", "grf";
			power-domains = <&power RK3399_PD_VIO>;
			#phy-cells = <0>;
			status = "disabled";
		};

		u2phy0: usb2-phy@e450 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe450 0x10>;
			clocks = <&cru SCLK_USB2PHY0_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "clk_usbphy0_480m";
			status = "disabled";

			u2phy0_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
			};

			u2phy0_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
						  "linestate";
				status = "disabled";
			};
		};

		u2phy1: usb2-phy@e460 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe460 0x10>;
			clocks = <&cru SCLK_USB2PHY1_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "clk_usbphy1_480m";
			status = "disabled";

			u2phy1_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
			};

			u2phy1_otg: otg-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "otg-bvalid", "otg-id",
						  "linestate";
				status = "disabled";
			};
		};

		emmc_phy: phy@f780 {
			compatible = "rockchip,rk3399-emmc-phy";
			reg = <0xf780 0x24>;
			clocks = <&sdhci>;
			clock-names = "emmcclk";
			#phy-cells = <0>;
			status = "disabled";
		};

		pcie_phy: pcie-phy {
			compatible = "rockchip,rk3399-pcie-phy";
			clocks = <&cru SCLK_PCIEPHY_REF>;
			clock-names = "refclk";
			#phy-cells = <1>;
			resets = <&cru SRST_PCIEPHY>;
			drive-impedance-ohm = <50>;
			reset-names = "phy";
			status = "disabled";
		};
	};

	tcphy0: phy@ff7c0000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff7c0000 0x0 0x40000>;
		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		power-domains = <&power RK3399_PD_TCPD0>;
		resets = <&cru SRST_UPHY0>,
			 <&cru SRST_UPHY0_PIPE_L00>,
			 <&cru SRST_P_UPHY0_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
		rockchip,grf = <&grf>;
		status = "disabled";

		tcphy0_dp: dp-port {
			#phy-cells = <0>;
		};

		tcphy0_usb3: usb3-port {
			#phy-cells = <0>;
		};
	};

	tcphy1: phy@ff800000 {
		compatible = "rockchip,rk3399-typec-phy";
		reg = <0x0 0xff800000 0x0 0x40000>;
		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
		clock-names = "tcpdcore", "tcpdphy-ref";
		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
		assigned-clock-rates = <50000000>;
		power-domains = <&power RK3399_PD_TCPD1>;
		resets = <&cru SRST_UPHY1>,
			 <&cru SRST_UPHY1_PIPE_L00>,
			 <&cru SRST_P_UPHY1_TCPHY>;
		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
		rockchip,grf = <&grf>;
		status = "disabled";

		tcphy1_dp: dp-port {
			#phy-cells = <0>;
		};

		tcphy1_usb3: usb3-port {
			#phy-cells = <0>;
		};
	};

	watchdog@ff848000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0xff848000 0x0 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	rktimer: rktimer@ff850000 {
		compatible = "rockchip,rk3399-timer";
		reg = <0x0 0xff850000 0x0 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
		clock-names = "pclk", "timer";
	};

	spdif: spdif@ff870000 {
		compatible = "rockchip,rk3399-spdif";
		reg = <0x0 0xff870000 0x0 0x1000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 7>;
		dma-names = "tx";
		clock-names = "mclk", "hclk";
		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_bus>;
		power-domains = <&power RK3399_PD_SDIOAUDIO>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s0: i2s@ff880000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff880000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_8ch_bus>;
		power-domains = <&power RK3399_PD_SDIOAUDIO>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s1: i2s@ff890000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff890000 0x0 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 2>, <&dmac_bus 3>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_2ch_bus>;
		power-domains = <&power RK3399_PD_SDIOAUDIO>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	i2s2: i2s@ff8a0000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff8a0000 0x0 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 4>, <&dmac_bus 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
		power-domains = <&power RK3399_PD_SDIOAUDIO>;
		#sound-dai-cells = <0>;
		status = "disabled";
	};

	vopl: vop@ff8f0000 {
		compatible = "rockchip,rk3399-vop-lit";
		reg = <0x0 0xff8f0000 0x0 0x3efc>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
		assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
		assigned-clock-rates = <400000000>, <100000000>;
		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		iommus = <&vopl_mmu>;
		power-domains = <&power RK3399_PD_VOPL>;
		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vopl_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vopl_out_mipi: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&mipi_in_vopl>;
			};

			vopl_out_edp: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&edp_in_vopl>;
			};

			vopl_out_hdmi: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&hdmi_in_vopl>;
			};

			vopl_out_mipi1: endpoint@3 {
				reg = <3>;
				remote-endpoint = <&mipi1_in_vopl>;
			};

			vopl_out_dp: endpoint@4 {
				reg = <4>;
				remote-endpoint = <&dp_in_vopl>;
			};
		};
	};

	vopl_mmu: iommu@ff8f3f00 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff8f3f00 0x0 0x100>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vopl_mmu";
		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3399_PD_VOPL>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	vopb: vop@ff900000 {
		compatible = "rockchip,rk3399-vop-big";
		reg = <0x0 0xff900000 0x0 0x3efc>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
		assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
		assigned-clock-rates = <400000000>, <100000000>;
		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		iommus = <&vopb_mmu>;
		power-domains = <&power RK3399_PD_VOPB>;
		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
		reset-names = "axi", "ahb", "dclk";
		status = "disabled";

		vopb_out: port {
			#address-cells = <1>;
			#size-cells = <0>;

			vopb_out_edp: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&edp_in_vopb>;
			};

			vopb_out_mipi: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&mipi_in_vopb>;
			};

			vopb_out_hdmi: endpoint@2 {
				reg = <2>;
				remote-endpoint = <&hdmi_in_vopb>;
			};

			vopb_out_mipi1: endpoint@3 {
				reg = <3>;
				remote-endpoint = <&mipi1_in_vopb>;
			};

			vopb_out_dp: endpoint@4 {
				reg = <4>;
				remote-endpoint = <&dp_in_vopb>;
			};
		};
	};

	vopb_mmu: iommu@ff903f00 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff903f00 0x0 0x100>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "vopb_mmu";
		clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
		clock-names = "aclk", "iface";
		power-domains = <&power RK3399_PD_VOPB>;
		#iommu-cells = <0>;
		status = "disabled";
	};

	isp0_mmu: iommu@ff914000 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "isp0_mmu";
		clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3399_PD_ISP0>;
		rockchip,disable-mmu-reset;
	};

	isp1_mmu: iommu@ff924000 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "isp1_mmu";
		clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
		clock-names = "aclk", "iface";
		#iommu-cells = <0>;
		power-domains = <&power RK3399_PD_ISP1>;
		rockchip,disable-mmu-reset;
	};

	hdmi_sound: hdmi-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,mclk-fs = <256>;
		simple-audio-card,name = "hdmi-sound";
		status = "disabled";

		simple-audio-card,cpu {
			sound-dai = <&i2s2>;
		};
		simple-audio-card,codec {
			sound-dai = <&hdmi>;
		};
	};

	hdmi: hdmi@ff940000 {
		compatible = "rockchip,rk3399-dw-hdmi";
		reg = <0x0 0xff940000 0x0 0x20000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru PCLK_HDMI_CTRL>,
			 <&cru SCLK_HDMI_SFR>,
			 <&cru PLL_VPLL>,
			 <&cru PCLK_VIO_GRF>,
			 <&cru SCLK_HDMI_CEC>;
		clock-names = "iahb", "isfr", "vpll", "grf", "cec";
		power-domains = <&power RK3399_PD_HDCP>;
		reg-io-width = <4>;
		rockchip,grf = <&grf>;
		#sound-dai-cells = <0>;
		status = "disabled";

		ports {
			hdmi_in: port {
				#address-cells = <1>;
				#size-cells = <0>;

				hdmi_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_hdmi>;
				};
				hdmi_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_hdmi>;
				};
			};
		};
	};

	mipi_dsi: mipi@ff960000 {
		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
		reg = <0x0 0xff960000 0x0 0x8000>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
			 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
		clock-names = "ref", "pclk", "phy_cfg", "grf";
		power-domains = <&power RK3399_PD_VIO>;
		resets = <&cru SRST_P_MIPI_DSI0>;
		reset-names = "apb";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			mipi_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				mipi_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_mipi>;
				};
				mipi_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_mipi>;
				};
			};
		};
	};

	mipi_dsi1: mipi@ff968000 {
		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
		reg = <0x0 0xff968000 0x0 0x8000>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
			 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
		clock-names = "ref", "pclk", "phy_cfg", "grf";
		power-domains = <&power RK3399_PD_VIO>;
		resets = <&cru SRST_P_MIPI_DSI1>;
		reset-names = "apb";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			mipi1_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				mipi1_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_mipi1>;
				};

				mipi1_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_mipi1>;
				};
			};
		};
	};

	edp: edp@ff970000 {
		compatible = "rockchip,rk3399-edp";
		reg = <0x0 0xff970000 0x0 0x8000>;
		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
		clock-names = "dp", "pclk", "grf";
		pinctrl-names = "default";
		pinctrl-0 = <&edp_hpd>;
		power-domains = <&power RK3399_PD_EDP>;
		resets = <&cru SRST_P_EDP_CTRL>;
		reset-names = "dp";
		rockchip,grf = <&grf>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			edp_in: port@0 {
				reg = <0>;
				#address-cells = <1>;
				#size-cells = <0>;

				edp_in_vopb: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&vopb_out_edp>;
				};

				edp_in_vopl: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&vopl_out_edp>;
				};
			};
		};
	};

	gpu: gpu@ff9a0000 {
		compatible = "rockchip,rk3399-mali", "arm,mali-t860";
		reg = <0x0 0xff9a0000 0x0 0x10000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
		interrupt-names = "job", "mmu", "gpu";
		clocks = <&cru ACLK_GPU>;
		#cooling-cells = <2>;
		power-domains = <&power RK3399_PD_GPU>;
		status = "disabled";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3399-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio0@ff720000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff720000 0x0 0x100>;
			clocks = <&pmucru PCLK_GPIO0_PMU>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio1: gpio1@ff730000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff730000 0x0 0x100>;
			clocks = <&pmucru PCLK_GPIO1_PMU>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio2: gpio2@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff780000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO2>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio3: gpio3@ff788000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff788000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO3>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio4: gpio4@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff790000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO4>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};