Skip to content
  1. Feb 17, 2021
  2. Nov 08, 2020
  3. Jul 18, 2020
  4. Jul 01, 2020
  5. Jun 17, 2020
  6. May 19, 2020
  7. May 05, 2020
  8. Apr 28, 2020
  9. Apr 19, 2020
  10. Mar 17, 2020
  11. Mar 11, 2020
  12. Mar 01, 2020
  13. Jan 19, 2020
  14. Dec 13, 2019
  15. Oct 05, 2019
  16. Jun 27, 2019
    • Enric Balletbo i Serra's avatar
      arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs · e6d237fd
      Enric Balletbo i Serra authored
      As per binding documentation [1], the DWC3 core should have the "ref",
      "bus_early" and "suspend" clocks. As explained in the binding, those
      clocks are required for new platforms but not for existing platforms
      before commit fe8abf33
      
       ("usb: dwc3: support clocks and resets for
      DWC3 core").
      
      However, as those clocks are really treated as required, this ends with
      having some annoying messages when the "rockchip,rk3399-dwc3" is used:
      
      [    1.724107] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
      [    1.731893] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
      [    2.495937] dwc3 fe800000.dwc3: Failed to get clk 'ref': -2
      [    2.647239] dwc3 fe900000.dwc3: Failed to get clk 'ref': -2
      
      In order to remove those annoying messages, update the DWC3 hardware
      module node and add all the required clocks. With this change, both, the
      glue node and the DWC3 core node, have the clocks defined, but that's
      not really a problem and there isn't a side effect on do this. So, we
      can get rid of the annoying get clk error messages.
      
      [1] Documentation/devicetree/bindings/usb/dwc3.txt
      
      Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      e6d237fd
    • Daniel Lezcano's avatar
      arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi · 95f231f8
      Daniel Lezcano authored
      
      
      Currently the common thermal zones definitions for the rk3399 assumes
      multiple thermal zones are supported by the governors. This is not the
      case and each thermal zone has its own governor instance acting
      individually without collaboration with other governors.
      
      As the cooling device for the CPU and the GPU thermal zones is the
      same, each governors take different decisions for the same cooling
      device leading to conflicting instructions and an erratic behavior.
      
      As the cooling-maps is about to become an optional property, let's
      remove the cpu cooling device map from the GPU thermal zone.
      
      Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      95f231f8
  17. Jun 04, 2019
  18. Apr 11, 2019
    • Katsuhiro Suzuki's avatar
      arm64: dts: rockchip: fix cts, rts pin assign of UART3 for rk3399 · 40a0dd42
      Katsuhiro Suzuki authored
      
      
      This patch fixes pin assign of cts and rts signal of UART3.
      
      Currently GPIO3_C2 and C3 pins are assigned but TRM says that
      GPIO3_C0 and C1 are correct.
      
      Refer:
        RK3399 TRM v1.4 - Table 19-1 UART Interface Description
      
      Signed-off-by: default avatarKatsuhiro Suzuki <katsuhiro@katsuster.net>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      40a0dd42
    • Heiko Stuebner's avatar
      arm64: dts: rockchip: bulk convert gpios to their constant counterparts · d64420e8
      Heiko Stuebner authored
      
      
      Rockchip SoCs use 2 different numbering schemes. Where the gpio-
      controllers just count 0-31 for their 32 gpios, the underlying
      iomux controller splits these into 4 separate entities A-D.
      
      Device-schematics always use these iomux-values to identify pins,
      so to make mapping schematics to devicetree easier Andy Yan introduced
      named constants for the pins but so far we only used them on new
      additions.
      
      Using a sed-script created by Emil Renner Berthing bulk-convert
      the remaining raw gpio numbers into their descriptive counterparts
      and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
      mappings:
      
      /rockchip,pins *=/bcheck
      b # to end of script
      :append-next-line
      N
      :check
      /^[^;]*$/bappend-next-line
      s/<RK_GPIO\([0-9]\) /<\1 /g
      s/<\([^ ][^ ]*  *\)0 /<\1RK_PA0 /g
      s/<\([^ ][^ ]*  *\)1 /<\1RK_PA1 /g
      s/<\([^ ][^ ]*  *\)2 /<\1RK_PA2 /g
      s/<\([^ ][^ ]*  *\)3 /<\1RK_PA3 /g
      s/<\([^ ][^ ]*  *\)4 /<\1RK_PA4 /g
      s/<\([^ ][^ ]*  *\)5 /<\1RK_PA5 /g
      s/<\([^ ][^ ]*  *\)6 /<\1RK_PA6 /g
      s/<\([^ ][^ ]*  *\)7 /<\1RK_PA7 /g
      s/<\([^ ][^ ]*  *\)8 /<\1RK_PB0 /g
      s/<\([^ ][^ ]*  *\)9 /<\1RK_PB1 /g
      s/<\([^ ][^ ]*  *\)10 /<\1RK_PB2 /g
      s/<\([^ ][^ ]*  *\)11 /<\1RK_PB3 /g
      s/<\([^ ][^ ]*  *\)12 /<\1RK_PB4 /g
      s/<\([^ ][^ ]*  *\)13 /<\1RK_PB5 /g
      s/<\([^ ][^ ]*  *\)14 /<\1RK_PB6 /g
      s/<\([^ ][^ ]*  *\)15 /<\1RK_PB7 /g
      s/<\([^ ][^ ]*  *\)16 /<\1RK_PC0 /g
      s/<\([^ ][^ ]*  *\)17 /<\1RK_PC1 /g
      s/<\([^ ][^ ]*  *\)18 /<\1RK_PC2 /g
      s/<\([^ ][^ ]*  *\)19 /<\1RK_PC3 /g
      s/<\([^ ][^ ]*  *\)20 /<\1RK_PC4 /g
      s/<\([^ ][^ ]*  *\)21 /<\1RK_PC5 /g
      s/<\([^ ][^ ]*  *\)22 /<\1RK_PC6 /g
      s/<\([^ ][^ ]*  *\)23 /<\1RK_PC7 /g
      s/<\([^ ][^ ]*  *\)24 /<\1RK_PD0 /g
      s/<\([^ ][^ ]*  *\)25 /<\1RK_PD1 /g
      s/<\([^ ][^ ]*  *\)26 /<\1RK_PD2 /g
      s/<\([^ ][^ ]*  *\)27 /<\1RK_PD3 /g
      s/<\([^ ][^ ]*  *\)28 /<\1RK_PD4 /g
      s/<\([^ ][^ ]*  *\)29 /<\1RK_PD5 /g
      s/<\([^ ][^ ]*  *\)30 /<\1RK_PD6 /g
      s/<\([^ ][^ ]*  *\)31 /<\1RK_PD7 /g
      s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)0 /<\1RK_FUNC_GPIO /g
      s/<\([^ ][^ ]*  *[^ ][^ ]*  *\)RK_FUNC_\([1-9]\) /<\1\2 /g
      
      Suggested-by: default avatarEmil Renner Berthing <esmil@mailme.dk>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      Tested-by: default avatarKatsuhiro Suzuki <katsuhiro@katsuster.net>
      Acked-by: default avatarRobin Murphy <robin.murphy@arm.com>
      d64420e8
  19. Mar 27, 2019
    • Christoph Muellner's avatar
      arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy. · fb8b7460
      Christoph Muellner authored
      
      
      A previous patch introduced the property 'drive-impedance-ohm'
      for the RK3399's emmc phy node. This patch sets this value
      explicitly to the default value of 50 Ohm.
      
      Signed-off-by: default avatarChristoph Muellner <christoph.muellner@theobroma-systems.com>
      Signed-off-by: default avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      fb8b7460
    • Christoph Muellner's avatar
      arm64: dts: rockchip: Disable DCMDs on RK3399's eMMC controller. · a3eec13b
      Christoph Muellner authored
      
      
      When using direct commands (DCMDs) on an RK3399, we get spurious
      CQE completion interrupts for the DCMD transaction slot (#31):
      
      [  931.196520] ------------[ cut here ]------------
      [  931.201702] mmc1: cqhci: spurious TCN for tag 31
      [  931.206906] WARNING: CPU: 0 PID: 1433 at /usr/src/kernel/drivers/mmc/host/cqhci.c:725 cqhci_irq+0x2e4/0x490
      [  931.206909] Modules linked in:
      [  931.206918] CPU: 0 PID: 1433 Comm: irq/29-mmc1 Not tainted 4.19.8-rt6-funkadelic #1
      [  931.206920] Hardware name: Theobroma Systems RK3399-Q7 SoM (DT)
      [  931.206924] pstate: 40000005 (nZcv daif -PAN -UAO)
      [  931.206927] pc : cqhci_irq+0x2e4/0x490
      [  931.206931] lr : cqhci_irq+0x2e4/0x490
      [  931.206933] sp : ffff00000e54bc80
      [  931.206934] x29: ffff00000e54bc80 x28: 0000000000000000
      [  931.206939] x27: 0000000000000001 x26: ffff000008f217e8
      [  931.206944] x25: ffff8000f02ef030 x24: ffff0000091417b0
      [  931.206948] x23: ffff0000090aa000 x22: ffff8000f008b000
      [  931.206953] x21: 0000000000000002 x20: 000000000000001f
      [  931.206957] x19: ffff8000f02ef018 x18: ffffffffffffffff
      [  931.206961] x17: 0000000000000000 x16: 0000000000000000
      [  931.206966] x15: ffff0000090aa6c8 x14: 0720072007200720
      [  931.206970] x13: 0720072007200720 x12: 0720072007200720
      [  931.206975] x11: 0720072007200720 x10: 0720072007200720
      [  931.206980] x9 : 0720072007200720 x8 : 0720072007200720
      [  931.206984] x7 : 0720073107330720 x6 : 00000000000005a0
      [  931.206988] x5 : ffff00000860d4b0 x4 : 0000000000000000
      [  931.206993] x3 : 0000000000000001 x2 : 0000000000000001
      [  931.206997] x1 : 1bde3a91b0d4d900 x0 : 0000000000000000
      [  931.207001] Call trace:
      [  931.207005]  cqhci_irq+0x2e4/0x490
      [  931.207009]  sdhci_arasan_cqhci_irq+0x5c/0x90
      [  931.207013]  sdhci_irq+0x98/0x930
      [  931.207019]  irq_forced_thread_fn+0x2c/0xa0
      [  931.207023]  irq_thread+0x114/0x1c0
      [  931.207027]  kthread+0x128/0x130
      [  931.207032]  ret_from_fork+0x10/0x20
      [  931.207035] ---[ end trace 0000000000000002 ]---
      
      The driver shows this message only for the first spurious interrupt
      by using WARN_ONCE(). Changing this to WARN() shows, that this is
      happening quite frequently (up to once a second).
      
      Since the eMMC 5.1 specification, where CQE and CQHCI are specified,
      does not mention that spurious TCN interrupts for DCMDs can be simply
      ignored, we must assume that using this feature is not working reliably.
      
      The current implementation uses DCMD for REQ_OP_FLUSH only, and
      I could not see any performance/power impact when disabling
      this optional feature for RK3399.
      
      Therefore this patch disables DCMDs for RK3399.
      
      Signed-off-by: default avatarChristoph Muellner <christoph.muellner@theobroma-systems.com>
      Signed-off-by: default avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
      Fixes: 84362d79
      
       ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1")
      Cc: stable@vger.kernel.org
      [the corresponding code changes are queued for 5.2 so doing that as well]
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      a3eec13b
  20. Mar 18, 2019
  21. Jan 31, 2019
  22. Dec 06, 2018
  23. Nov 19, 2018
    • Viresh Kumar's avatar
      arm64: dts: rockchip: Add all CPUs in cooling maps · cdd46460
      Viresh Kumar authored
      
      
      Each CPU can (and does) participate in cooling down the system but the
      DT only captures a handful of them, normally CPU0, in the cooling maps.
      Things work by chance currently as under normal circumstances its the
      first CPU of each cluster which is used by the operating systems to
      probe the cooling devices. But as soon as this CPU ordering changes and
      any other CPU is used to bring up the cooling device, we will start
      seeing failures.
      
      Also the DT is rather incomplete when we list only one CPU in the
      cooling maps, as the hardware doesn't have any such limitations.
      
      Update cooling maps to include all devices affected by individual trip
      points.
      
      Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      cdd46460
  24. Nov 05, 2018
  25. Sep 26, 2018
  26. Aug 29, 2018
  27. Jul 25, 2018
  28. Jul 04, 2018
  29. Jun 20, 2018
  30. Jun 17, 2018
  31. Apr 16, 2018