rk3399.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
 */

#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3399-power.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "rockchip,rk3399";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		ethernet0 = &gmac;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		mmc0 = &sdio0;
		mmc1 = &sdmmc;
		mmc2 = &sdhci;
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu_l0>;
				};
				core1 {
					cpu = <&cpu_l1>;
				};
				core2 {
					cpu = <&cpu_l2>;
				};
				core3 {
					cpu = <&cpu_l3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu_b0>;
				};
				core1 {
					cpu = <&cpu_b1>;
				};
			};
		};

		cpu_l0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <485>;
			clocks = <&cru ARMCLKL>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <100>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		cpu_l1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			capacity-dmips-mhz = <485>;
			clocks = <&cru ARMCLKL>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <100>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		cpu_l2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			enable-method = "psci";
			capacity-dmips-mhz = <485>;
			clocks = <&cru ARMCLKL>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <100>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		cpu_l3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			enable-method = "psci";
			capacity-dmips-mhz = <485>;
			clocks = <&cru ARMCLKL>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <100>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		cpu_b0: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&cru ARMCLKB>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <436>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		cpu_b1: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0 0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			clocks = <&cru ARMCLKB>;
			#cooling-cells = <2>; /* min followed by max */
			dynamic-power-coefficient = <436>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <120>;
				exit-latency-us = <250>;
				min-residency-us = <900>;
			};

			CLUSTER_SLEEP: cluster-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <400>;
				exit-latency-us = <500>;
				min-residency-us = <2000>;
			};
		};
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <&vopl_out>, <&vopb_out>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
	};

	pmu_a72 {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
		arm,no-tick-in-suspend;
	};

	xin24m: xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;