- Sep 29, 2023
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Iago Toral Quiroga authored
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Phil Elwell authored
The built-in MMU driver went most of the way towards supporting larger kernel pages, but dropped the ball when it comes to calculating indexes into the page table. Fix it. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Iago Toral Quiroga authored
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Iago Toral Quiroga authored
V3D t.x takes a new parameter to configure TFU jobs that needs to be provided by user space.
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Iago Toral Quiroga authored
v2: fix kernel panic with debug-fs interface to list registers
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Nick Hollinghurst authored
Formerly the delay was omitted as bit-banged SPI seldom achieved even one Mbit/s; but some modern platforms can run faster, and some SPI devices may need to be clocked slower. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Nick Hollinghurst authored
Formerly, if configured using DT, CS GPIOs were driven from spi.c and it was possible for CS to be asserted (low) *before* starting to drive SCK. CS GPIOs have been brought under control of this driver in both ACPI and DT cases, with a fixup for GPIO polarity. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Phil Elwell authored
BCM2712 has a PM block but neither ASB nor RPIVID_ASB. Use the absence of the "asb" register range to indicate BCM2712 and its different PM register range. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
BCM2712 lacks the "asb" and "rpivid_asb" register ranges, but still requires the use of the bcm2835-power driver to reset the V3D block. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
These soundcard drivers don't rely on a specific I2S interface, so remove the dependency declarations. See: https://github.com/raspberrypi/linux-2712/issues/111 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
IMO the Synopsys datasheet could be clearer in this area, but it seems that the DMA data ports (DMATX and DMARX) expect left and right samples in alternate writes; if a stereo pair is pushed in a single 32-bit write, the upper half is ignored, leading to double speed audio with a confused stereo image. Make sure the necessary changes happen by updating the DMA configuration data in the hw_params method. The set_bclk_ratio change was made at a time when it looked like it could be causing an error, but I think the division of responsibilities is clearer this way (and the kernel log clearer without the info-level message). Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Disabling the I2S interface with outstanding transfers prevents the DMAC from shutting down, so keep it partially active after a stop. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Add control of the DMACR register, which is required for paced DMA (i.e. DREQ) support. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
The hardware configuration determines the maximum-supported sample size for each channel, but TCRx allows smaller sizes to be specified at run time. Include the smaller supported sizes in the formats array. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Add optional properties to tune the AXI interface - cdns,aw2w-max-pipe, cdns,ar2r-max-pipe and cdns,use-aw2b-fill. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Naushir Patuck authored
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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Naushir Patuck authored
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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Nick Hollinghurst authored
Add support for the RP1 VEC hardware. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Nick Hollinghurst authored
Add support for the RP1 DPI hardware. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Nick Hollinghurst authored
Add support for the RP1 DSI hardware. Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Phil Elwell authored
Add a driver for the RP1 PWM block. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Don't assume that DMA addresses of devices are the same as their physical addresses - convert correctly. The CFG2 register layout is used when there are more than 8 channels, but also when configured for more than 16 target peripheral devices because the index of the handshake signal has to be made wider. Reset the DMAC on probe The driver goes to the trouble of tracking when transfers have been paused, but then doesn't report that state when queried. Not having APB registers is not an error - for most use cases it's not even of interest, it's expected. Demote the message to debug level, which is disabled by default. Each channel has a descriptor pool, which is shared between transfers. It is unsafe to treat the total number of descriptors allocated from a pool as the number allocated to a specific transfer; doing so leads to releasing buffers that shouldn't be released and walking off the ends of descriptor lists. Instead, give each transfer descriptor its own count. Support partial transfers: Some use cases involve streaming from a device where the transfer only proceeds when the device's FIFO occupancy exceeds a certain threshold. In such cases (e.g. when pulling data from a UART) it is important to know how much data has been transferred so far, in order that remaining bytes can be read from the FIFO directly by software. Add the necessary code to provide this "residue" value with a finer, sub-transfer granularity. In order to prevent the occasional byte getting stuck in the DMA controller's internal buffers, restrict the destination memory width to the source register width. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
The SMBUS emulation code turns an SMBUS quick command into a zero- length read. This controller can't do zero length accesses, but it can do quick commands, so reverse the emulation. The alternative would be to properly implement the SMBUS support but that is a lot more work, and unnecessary just to get i2cdetect working. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Liam Fraser authored
Signed-off-by: Liam Fraser <liam@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
RP1 exposes GPIOs. Add a pinctrl driver to allow control of those. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
RP1 contains various PLLs and clocks for driving the hardware blocks, so add a driver to configure these. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
RP1 is a multifunction PCIe device that exposes a range of peripherals. Add the parent driver to manage these. Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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Phil Elwell authored
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Naushir Patuck authored
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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Naushir Patuck authored
Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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Jim Quinlan authored
PCI: brcmstb: differing register offsets on 2712 pcie-brcmstb: Add 2712 bridge reset support pcie: 2712 PORT_MASK and rescal support pcie-brcmstb: don't alter the L1SS debug register For reasons unknown, this disables the reference clock pcie-brcmstb: fix BAR2 enable and window decode Set UBUS ACCESS_EN to let inbound DMA work. Also BCM2712 has grown an index in the inbound window size decode register. PCIe: brcmstb: Enable support for 64 MSI-Xs Signed-off-by: Phil Elwell <phil@raspberrypi.com> pcie-brcmstb: Suppress read error responses If the link is down or the EP fails to return a read completion, the RC's default behaviour is to return an AXI error. This causes fatal exceptions on A76, so it's better to respond with all 1s instead. pcie-brcmstb: increase UBUS timeout to cater for link retrain events pcie-brcmstb: Handle additional inbound regions Signed-off-by: Phil Elwell <phil@raspberrypi.com> pcie-brcmstb: Add support for external MSI controller pcie-brcmstb: add a reasonable default traffic class to priority map BCM2712 supports multiple traffic classes (TCs) with independent maximally sized transfer queues for each TC. Traffic classes have no transaction ordering requirements between them, which facilitates out-of-order completions and arbitration between posted writes for data streams that have no dependence on each other. In addition to the above benefits of splitting endpoint traffic into individual queues, priorities can be assigned to traffic classes by a heuristic or deterministic mechanism. The heuristic elevates AXI QOS priority in accordance with the number of pending transfers in each TC's queue, but for true priority signalling a forwarding mechanism using vendor-defined messages is implemented. Receipt of a 3 DWORD VDM assigns a priority tag to a TC on-the-fly, and this tag corresponds to a configurable AXI QOS value. As a simple baseline, assign a linear map of AXI QOS to each tag. pcie: brcmstb: set up the VDM forwarding interface when setting up QoS pcie-brcmstb: add DT bindings for MPS-size Read Completion Mode This controller has an optional feature that allows read completion TLPs to be sized up to the Maximum Packet Size of a configured link. This can exceed the Read Completion Boundary of 128B specified in the PCIe specification, but depending on endpoint support may increase link read bandwidth significantly. pcie-brcmstb: clean up debug messages pcie-brcmstb: fix BCM2712A0 PHY PM errata The power management clock is 54MHz not 50MHz, so adjust the PM clock period to suit. Powering off the PHY PLL in L1.2 is unsafe, so force it on. pcie-brcmstb: set CLKREQ functionality according to link partner support The RC supports either L1 with clock PM or L1 sub-state control, not both at the same time. Examine the link partner's capabilities to determine which is the most suitable scheme to use. pcie: brcmstb: don't reset block bridges in suspend or removal cases BCM2712 has a single rescal block for all three root complexes, and holding PCIE1's bridge in reset will hang the chip if a different RC wants to access any of the rescal registers. pcie: brcmstb: guard 2712-specific setup with a RC type check BCM2711 doesn't implement the UBUS control registers. pcie: brcmstb: On 2712 keeping the PLL powered in L1.x is not required A separate misconfiguration when enabling SSC (the MDIO registers no longer do the same thing on BCM2712) had the side-effect of breaking PLL powerdown and resume sequencing. Allow entry into a true L1.2 state where analogue is depowered. pcie: brcmstb: Fix reset warning on probe failure Signed-off-by: Phil Elwell <phil@raspberrypi.com> bcm2712: pcie: adjust PHY PLL setup to use a 54MHz input refclk Use canned MDIO writes from Broadcom that switch the ref_clk output pair to run from the internal fractional PLL, and set the internal PLL to expect a 54MHz input reference clock. Gen3 operation is not guaranteed to be stable in this setup, so default to gen2. This only works if the LCPLL is bypassed (requires latest bootloader). pcie: brcmstb: add missing register writes drivers: pcie: brcmstb: cater for BCM2712C0 bug dropping QoS on the floor The AXI QoS value extracted from the request fifo ends up as zero forever. Disabling this means that "panic" signalling doesn't do anything useful, but static priorites do work. Also align the selected TC:QoS map with RP1's expectations of service. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> drivers: pcie: brcmstb: shuffle TC priorities up to 8 Use the range 8-11 which puts the highest below HVS but leaves space below for other 2712 masters. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> drivers: pcie: brcmstb: optionally enable QoS features by DT for BCM2712 It's a bad idea to universally enable "realtime" priorities for TCs across all the RC instances on the chip. Endpoints other than RP1 may make use of these, so you don't want e.g. NVMe descriptor fetches getting higher priority than your remote display. Add two optional DT properties controlling the behaviour - FIFO-based backpressure QoS or "message-based". Message-based signalling is fundamentally broken due to a chip bug, so it collapses into a set of static assignments that RP1 needs. The default if neither property is specified is to assign everything a QoS of 0. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com> drivers: pcie: brcmstb: adjust completion timeouts for bcm2712 Setting the RC config retry timeout makes CRS auto-polling work, but the UBUS timeout will override the config retry. Both need to be large. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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