dmaengine: dw-axi-dmac: Fixes for RP1

Don't assume that DMA addresses of devices are the same as their
physical addresses - convert correctly.

The CFG2 register layout is used when there are more than 8 channels,
but also when configured for more than 16 target peripheral devices
because the index of the handshake signal has to be made wider.

Reset the DMAC on probe

The driver goes to the trouble of tracking when transfers have been
paused, but then doesn't report that state when queried.

Not having APB registers is not an error - for most use cases it's
not even of interest, it's expected. Demote the message to debug level,
which is disabled by default.

Each channel has a descriptor pool, which is shared between transfers.
It is unsafe to treat the total number of descriptors allocated from a
pool as the number allocated to a specific transfer; doing so leads
to releasing buffers that shouldn't be released and walking off the
ends of descriptor lists. Instead, give each transfer descriptor its
own count.

Support partial transfers:
Some use cases involve streaming from a device where the transfer only
proceeds when the device's FIFO occupancy exceeds a certain threshold.
In such cases (e.g. when pulling data from a UART) it is important to
know how much data has been transferred so far, in order that remaining
bytes can be read from the FIFO directly by software.

Add the necessary code to provide this "residue" value with a finer,
sub-transfer granularity.

In order to prevent the occasional byte getting stuck in the DMA
controller's internal buffers, restrict the destination memory width
to the source register width.

Signed-off-by: Phil Elwell <phil@raspberrypi.com>