PCI: brcmstb: Add BCM2712 support

PCI: brcmstb: differing register offsets on 2712

pcie-brcmstb: Add 2712 bridge reset support

pcie: 2712 PORT_MASK and rescal support

pcie-brcmstb: don't alter the L1SS debug register

For reasons unknown, this disables the reference clock

pcie-brcmstb: fix BAR2 enable and window decode

Set UBUS ACCESS_EN to let inbound DMA work. Also BCM2712 has grown
an index in the inbound window size decode register.

PCIe: brcmstb: Enable support for 64 MSI-Xs

Signed-off-by: Phil Elwell <phil@raspberrypi.com>

pcie-brcmstb: Suppress read error responses

If the link is down or the EP fails to return a read completion, the
RC's default behaviour is to return an AXI error. This causes fatal
exceptions on A76, so it's better to respond with all 1s instead.

pcie-brcmstb: increase UBUS timeout to cater for link retrain events

pcie-brcmstb: Handle additional inbound regions

Signed-off-by: Phil Elwell <phil@raspberrypi.com>

pcie-brcmstb: Add support for external MSI controller

pcie-brcmstb: add a reasonable default traffic class to priority map

BCM2712 supports multiple traffic classes (TCs) with independent
maximally sized transfer queues for each TC. Traffic classes have no
transaction ordering requirements between them, which facilitates
out-of-order completions and arbitration between posted writes for
data streams that have no dependence on each other.

In addition to the above benefits of splitting endpoint traffic into
individual queues, priorities can be assigned to traffic classes by
a heuristic or deterministic mechanism. The heuristic elevates AXI
QOS priority in accordance with the number of pending transfers in
each TC's queue, but for true priority signalling a forwarding
mechanism using vendor-defined messages is implemented.

Receipt of a 3 DWORD VDM assigns a priority tag to a TC on-the-fly,
and this tag corresponds to a configurable AXI QOS value.

As a simple baseline, assign a linear map of AXI QOS to each tag.

pcie: brcmstb: set up the VDM forwarding interface when setting up QoS

pcie-brcmstb: add DT bindings for MPS-size Read Completion Mode

This controller has an optional feature that allows read completion
TLPs to be sized up to the Maximum Packet Size of a configured link.

This can exceed the Read Completion Boundary of 128B specified in
the PCIe specification, but depending on endpoint support may increase
link read bandwidth significantly.

pcie-brcmstb: clean up debug messages

pcie-brcmstb: fix BCM2712A0 PHY PM errata

The power management clock is 54MHz not 50MHz, so adjust the PM clock period
to suit. Powering off the PHY PLL in L1.2 is unsafe, so force it on.

pcie-brcmstb: set CLKREQ functionality according to link partner support

The RC supports either L1 with clock PM or L1 sub-state control, not both
at the same time. Examine the link partner's capabilities to determine
which is the most suitable scheme to use.

pcie: brcmstb: don't reset block bridges in suspend or removal cases

BCM2712 has a single rescal block for all three root complexes, and
holding PCIE1's bridge in reset will hang the chip if a different
RC wants to access any of the rescal registers.

pcie: brcmstb: guard 2712-specific setup with a RC type check

BCM2711 doesn't implement the UBUS control registers.

pcie: brcmstb: On 2712 keeping the PLL powered in L1.x is not required

A separate misconfiguration when enabling SSC (the MDIO registers no
longer do the same thing on BCM2712) had the side-effect of breaking
PLL powerdown and resume sequencing.

Allow entry into a true L1.2 state where analogue is depowered.

pcie: brcmstb: Fix reset warning on probe failure

Signed-off-by: Phil Elwell <phil@raspberrypi.com>

bcm2712: pcie: adjust PHY PLL setup to use a 54MHz input refclk

Use canned MDIO writes from Broadcom that switch the ref_clk output
pair to run from the internal fractional PLL, and set the internal PLL
to expect a 54MHz input reference clock.

Gen3 operation is not guaranteed to be stable in this setup, so default
to gen2.

This only works if the LCPLL is bypassed (requires latest bootloader).

pcie: brcmstb: add missing register writes

drivers: pcie: brcmstb: cater for BCM2712C0 bug dropping QoS on the floor

The AXI QoS value extracted from the request fifo ends up as zero forever.
Disabling this means that "panic" signalling doesn't do anything useful,
but static priorites do work.

Also align the selected TC:QoS map with RP1's expectations of service.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>

drivers: pcie: brcmstb: shuffle TC priorities up to 8

Use the range 8-11 which puts the highest below HVS but leaves space
below for other 2712 masters.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>

drivers: pcie: brcmstb: optionally enable QoS features by DT for BCM2712

It's a bad idea to universally enable "realtime" priorities for TCs
across all the RC instances on the chip. Endpoints other than RP1 may
make use of these, so you don't want e.g. NVMe descriptor fetches getting
higher priority than your remote display.

Add two optional DT properties controlling the behaviour - FIFO-based
backpressure QoS or "message-based". Message-based signalling is
fundamentally broken due to a chip bug, so it collapses into a set of
static assignments that RP1 needs.

The default if neither property is specified is to assign everything a
QoS of 0.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>

drivers: pcie: brcmstb: adjust completion timeouts for bcm2712

Setting the RC config retry timeout makes CRS auto-polling work, but
the UBUS timeout will override the config retry. Both need to be large.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>