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  1. Mar 17, 2021
  2. Mar 16, 2021
    • David S. Miller's avatar
      Merge branch 'ionic-tx-updates' · 74c7dbe0
      David S. Miller authored
      
      
      Shannon Nelson says:
      
      ====================
      ionic Tx updates
      
      Just as the Rx path recently got a face lift, it is time for the Tx path to
      get some attention.  The original TSO-to-descriptor mapping was ugly and
      convoluted and needed some deep work.  This series pulls the dma mapping
      out of the descriptor frag mapping loop and makes the dma mapping more
      generic for use in the non-TSO case.
      ====================
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      74c7dbe0
    • Shannon Nelson's avatar
      ionic: aggregate Tx byte counting calls · 633eddf1
      Shannon Nelson authored
      
      
      Gather the Tx packet and byte counts and call
      netdev_tx_completed_queue() only once per clean cycle.
      
      Signed-off-by: default avatarShannon Nelson <snelson@pensando.io>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      633eddf1
    • Shannon Nelson's avatar
      ionic: simplify tx clean · 19fef72c
      Shannon Nelson authored
      
      
      The descriptor mappings are set up the same way whether
      or not it is a TSO, so we don't need separate logic for
      the two cases.
      
      Signed-off-by: default avatarShannon Nelson <snelson@pensando.io>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      19fef72c
    • Shannon Nelson's avatar
      ionic: generic tx skb mapping · 2da479ca
      Shannon Nelson authored
      
      
      Make the new ionic_tx_map_tso() usable by the non-TSO paths,
      and pull the call up a level into ionic_tx() before calling
      the csum or no-csum routines.
      
      Signed-off-by: default avatarShannon Nelson <snelson@pensando.io>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      2da479ca
    • Shannon Nelson's avatar
      ionic: simplify TSO descriptor mapping · 5b039241
      Shannon Nelson authored
      
      
      One issue with the original TSO code was that it was working too
      hard to deal with skb layouts that were never going to show up,
      such as an skb->data that was longer than a single descriptor's
      length.  The other issue was trying to arrange the fragment dma
      mapping at the same time as figuring out the descriptors needed.
      There was just too much going on at the same time.
      
      Now we do the dma mapping first, which sets up the buffers with
      skb->data in buf[0] and the remaining frags in buf[1..n-1].
      Next we spread the bufs across the descriptors needed, where
      each descriptor gets up to mss number of bytes.
      
      Signed-off-by: default avatarShannon Nelson <snelson@pensando.io>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5b039241
    • David S. Miller's avatar
      Merge branch 'net-qualcomm-rmnet-stop-using-C-bit-fields' · 578ce046
      David S. Miller authored
      
      
      Alex Elder says:
      
      ====================
      net: qualcomm: rmnet: stop using C bit-fields
      
      Version 6 is the same as version 5, but has been rebased on updated
      net-next/master.  With any luck, the patches I'm sending out this
      time won't contain garbage.
      
      Version 5 of this series responds to a suggestion made by Alexander
      Duyck, to determine the offset to the checksummed range of a packet
      using skb_network_header_len() on patch 2.  I have added his
      Reviewed-by tag to all (other) patches, and removed Bjorn's from
      patch 2.
      
      The change required some updates to the subsequent patches, and I
      reordered some assignments in a minor way in the last patch.
      
      I don't expect any more discussion on this series (but will respond
      if there is any).  So at this point I would really appreciate it
      if KS and/or Sean would offer a review, or at least acknowledge it.
      I presume you two are able to independently test the code as well,
      so I request that, and hope you are willing to do so.
      
      Version 4 of this series is here:
        https://lore.kernel.org/netdev/20210315133455.1576188-1-elder@linaro.org
      ====================
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      578ce046
    • Alex Elder's avatar
      net: qualcomm: rmnet: don't use C bit-fields in rmnet checksum header · 86ca860e
      Alex Elder authored
      
      
      Replace the use of C bit-fields in the rmnet_map_ul_csum_header
      structure with a single two-byte (big endian) structure member,
      and use masks to encode or get values within it.  The content of
      these fields can be accessed using simple bitwise AND and OR
      operations on the (host byte order) value of the new structure
      member.
      
      Previously rmnet_map_ipv4_ul_csum_header() would update C bit-field
      values in host byte order, then forcibly fix their byte order using
      a combination of byte swap operations and types.
      
      Instead, just compute the value that needs to go into the new
      structure member and save it with a simple byte-order conversion.
      
      Make similar simplifications in rmnet_map_ipv6_ul_csum_header().
      
      Finally, in rmnet_map_checksum_uplink_packet() a set of assignments
      zeroes every field in the upload checksum header.  Replace that with
      a single memset() operation.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      86ca860e
    • Alex Elder's avatar
      net: qualcomm: rmnet: don't use C bit-fields in rmnet checksum trailer · cc1b21ba
      Alex Elder authored
      
      
      Replace the use of C bit-fields in the rmnet_map_dl_csum_trailer
      structure with a single one-byte field, using constant field masks
      to encode or get at embedded values.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      cc1b21ba
    • Alex Elder's avatar
      net: qualcomm: rmnet: use masks instead of C bit-fields · 16653c16
      Alex Elder authored
      
      
      The actual layout of bits defined in C bit-fields (e.g. int foo : 3)
      is implementation-defined.  Structures defined in <linux/if_rmnet.h>
      address this by specifying all bit-fields twice, to cover two
      possible layouts.
      
      I think this pattern is repetitive and noisy, and I find the whole
      notion of compiler "bitfield endianness" to be non-intuitive.
      
      Stop using C bit-fields for the command/data flag and the pad length
      fields in the rmnet_map structure, and define a single-byte flags
      field instead.  Define a mask for the single-bit "command" flag,
      and another mask for the encoded pad length.  The content of both
      fields can be accessed using a simple bitwise AND operation.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      16653c16
    • Alex Elder's avatar
      net: qualcomm: rmnet: kill RMNET_MAP_GET_*() accessor macros · 9d131d04
      Alex Elder authored
      
      
      The following macros, defined in "rmnet_map.h", assume a socket
      buffer is provided as an argument without any real indication this
      is the case.
          RMNET_MAP_GET_MUX_ID()
          RMNET_MAP_GET_CD_BIT()
          RMNET_MAP_GET_PAD()
          RMNET_MAP_GET_CMD_START()
          RMNET_MAP_GET_LENGTH()
      What they hide is pretty trivial accessing of fields in a structure,
      and it's much clearer to see this if we do these accesses directly.
      
      So rather than using these accessor macros, assign a local
      variable of the map header pointer type to the socket buffer data
      pointer, and derereference that pointer variable.
      
      In "rmnet_map_data.c", use sizeof(object) rather than sizeof(type)
      in one spot.  Also, there's no need to byte swap 0; it's all zeros
      irrespective of endianness.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      9d131d04
    • Alex Elder's avatar
      net: qualcomm: rmnet: simplify some byte order logic · 50c62a11
      Alex Elder authored
      
      
      In rmnet_map_ipv4_ul_csum_header() and rmnet_map_ipv6_ul_csum_header()
      the offset within a packet at which checksumming should commence is
      calculated.  This calculation involves byte swapping and a forced type
      conversion that makes it hard to understand.
      
      Simplify this by computing the offset in host byte order, then
      converting the result when assigning it into the header field.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      50c62a11
    • Alex Elder's avatar
      net: qualcomm: rmnet: mark trailer field endianness · 45f3a13c
      Alex Elder authored
      
      
      The fields in the checksum trailer structure used for QMAP protocol
      RX packets are all big-endian format, so define them that way.
      
      It turns out these fields are never actually used by the RMNet code.
      The start offset is always assumed to be zero, and the length is
      taken from the other packet headers.  So making these fields
      explicitly big endian has no effect on the behavior of the code.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      45f3a13c
    • Alex Elder's avatar
      net: ipa: make ipa_table_hash_support() inline · 0f13b5e6
      Alex Elder authored
      
      
      In review, Alexander Duyck suggested that ipa_table_hash_support()
      was trivial enough that it could be implemented as a static inline
      function in the header file.  But the patch had already been
      accepted.  Implement his suggestion.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarAlexander Duyck <alexanderduyck@fb.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      0f13b5e6
    • Ivan Bornyakov's avatar
      net: phy: add Marvell 88X2222 transceiver support · 6e3bac3e
      Ivan Bornyakov authored
      
      
      Add basic support for the Marvell 88X2222 multi-speed ethernet
      transceiver.
      
      This PHY provides data transmission over fiber-optic as well as Twinax
      copper links. The 88X2222 supports 2 ports of 10GBase-R and 1000Base-X
      on the line-side interface. The host-side interface supports 4 ports of
      10GBase-R, RXAUI, 1000Base-X and 2 ports of XAUI.
      
      This driver, however, supports only XAUI on the host-side and
      1000Base-X/10GBase-R on the line-side, for now. The SGMII is also
      supported over 1000Base-X. Interrupts are not supported.
      
      Internal registers access compliant with the Clause 45 specification.
      
      Signed-off-by: default avatarIvan Bornyakov <i.bornyakov@metrotek.ru>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      6e3bac3e
    • David S. Miller's avatar
      Merge branch 'stmmac-clocks' · 63fe6059
      David S. Miller authored
      
      
      Joakim Zhang says:
      
      ====================
      net: stmmac: implement clocks management
      
      This patch set tries to implement clocks management, and takes i.MX platform as an example.
      
      ---
      ChangeLogs:
      V1->V2:
      	* change to pm runtime mechanism.
      	* rename function: _enable() -> _config()
      	* take MDIO bus into account, it needs clocks when interface
      	is closed.
      	* reverse Christmass tree.
      V2->V3:
      	* slightly simple the code according to Andrew's suggesstion
      	and also add tag: Reviewed-by: Andrew Lunn <andrew@lunn.ch>
      ====================
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      63fe6059
    • Joakim Zhang's avatar
      net: stmmac: dwmac-imx: add platform level clocks management for i.MX · 8f2f8376
      Joakim Zhang authored
      
      
      Split clocks settings from init callback into clks_config callback,
      which could support platform level clocks management.
      
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8f2f8376
    • Joakim Zhang's avatar
      net: stmmac: add platform level clocks management · b4d45aee
      Joakim Zhang authored
      
      
      This patch intends to add platform level clocks management. Some
      platforms may have their own special clocks, they also need to be
      managed dynamically. If you want to manage such clocks, please implement
      clks_config callback.
      
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      b4d45aee
    • Joakim Zhang's avatar
      net: stmmac: add clocks management for gmac driver · 5ec55823
      Joakim Zhang authored
      
      
      This patch intends to add clocks management for stmmac driver:
      
      If CONFIG_PM enabled:
      1. Keep clocks disabled after driver probed.
      2. Enable clocks when up the net device, and disable clocks when down
      the net device.
      
      If CONFIG_PM disabled:
      Keep clocks always enabled after driver probed.
      
      Note:
      1. It is fine for ethtool, since the way of implementing ethtool_ops::begin
      in stmmac is only can be accessed when interface is enabled, so the clocks
      are ticked.
      2. The MDIO bus has a different life cycle to the MAC, need ensure
      clocks are enabled when _mdio_read/write() need clocks, because these
      functions can be called while the interface it not opened.
      
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5ec55823
    • David S. Miller's avatar
      Merge branch 'net-pcs-stmmac=add-C37-AN-SGMII-support' · 91de5ac9
      David S. Miller authored
      
      
      Ong Boon Leong says:
      
      ====================
      net: pcs, stmmac: add C37 AN SGMII support
      
      This patch series adds MAC-side SGMII support to stmmac driver and it is
      changed as follow:-
      
      1/6: Refactor the current C73 implementation in pcs-xpcs to prepare for
           adding C37 AN later.
      2/6: Add MAC-side SGMII C37 AN support to pcs-xpcs
      3,4/6: make phylink_parse_mode() to work for non-DT platform so that
             we can use stmmac platform_data to set it.
      5/6: Make stmmac_open() to only skip PHY init if C73 is used, otherwise
           C37 AN will need phydev to be connected to phylink.
      6/6: Finally, add pcs-xpcs SGMII interface support to Intel mGbE
           controller.
      
      The patch series have been tested on EHL CRB PCH TSN (eth2) controller
      that has Marvell 88E1512 PHY attached over SGMII interface and the
      iterative tests of speed change (AN) + ping test have been successful.
      
      [63446.009295] intel-eth-pci 0000:00:1e.4 eth2: Link is Down
      [63449.986365] intel-eth-pci 0000:00:1e.4 eth2: Link is Up - 1Gbps/Full - flow control off
      [63449.987625] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
      [63451.248064] intel-eth-pci 0000:00:1e.4 eth2: Link is Down
      [63454.082366] intel-eth-pci 0000:00:1e.4 eth2: Link is Up - 100Mbps/Full - flow control off
      [63454.083650] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
      [63456.465179] intel-eth-pci 0000:00:1e.4 eth2: Link is Down
      [63459.202367] intel-eth-pci 0000:00:1e.4 eth2: Link is Up - 10Mbps/Full - flow control off
      [63459.203639] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
      [63460.882832] intel-eth-pci 0000:00:1e.4 eth2: Link is Down
      [63464.322366] intel-eth-pci 0000:00:1e.4 eth2: Link is Up - 1Gbps/Full - flow control off
      ====================
      
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      91de5ac9