- Jan 03, 2014
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Rohit Vaswani authored
This patch adds basic board support for APQ8074 Dragonboard which belongs to the Snapdragon 800 family. For now, just support a basic machine with device tree. Signed-off-by:
Rohit Vaswani <rvaswani@codeaurora.org> Acked-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
David Brown <davidb@codeaurora.org> [olof: Split off SoC and board support in separate patches] Signed-off-by:
Olof Johansson <olof@lixom.net>
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Stephen Boyd authored
Add the mmio architected timer node. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
David Brown <davidb@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Stephen Boyd authored
Add the restart node so we can reboot the device. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
David Brown <davidb@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Rohit Vaswani authored
Add support for the Snapdragon 800 MSM8974 SoC, used on the Dragonboard and others. Board support added in separate patch. Signed-off-by:
Rohit Vaswani <rvaswani@codeaurora.org> Acked-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
David Brown <davidb@codeaurora.org> [olof: split off SoC support in separate patch] Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Dec 04, 2013
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Dinh Nguyen authored
Some of the clocks that were designated gate-clk do not have a gate, so change those clocks to be of periph-clk type. Signed-off-by:
Dinh Nguyen <dinguyen@altera.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Dec 03, 2013
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Florian Vaussard authored
drivers/net/ethernet/smsc/smsc911x.c is expecting supplies named "vdd33a" and "vddvario". Currently the shared DTS file provides "vmmc" and "vmmc_aux", and the supply lookup will fail: smsc911x 2c000000.ethernet: Looking up vdd33a-supply from device tree smsc911x 2c000000.ethernet: Looking up vdd33a-supply property in node /ocp/gpmc@6e000000/ethernet@gpmc failed smsc911x 2c000000.ethernet: Looking up vddvario-supply from device tree smsc911x 2c000000.ethernet: Looking up vddvario-supply property in node /ocp/gpmc@6e000000/ethernet@gpmc failed Fix it! Looks like commmit 6b2978ac (ARM: dts: Shared file for omap GPMC connected smsc911x) made the problem more visible by moving the smc911x configuration from the omap3-igep0020.dts file to the generic file. But it seems we've had this problem since commit d72b4415 (ARM: dts: omap3-igep0020: Add SMSC911x LAN chip support). Tested on OMAP3 Overo platform. Signed-off-by:
Florian Vaussard <florian.vaussard@epfl.ch> [tony@atomide.com: updated comments for the commits causing the problem] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Jarkko Nikula authored
This adds typical McBSP2-TWL4030 audio description to the legacy Beagle Board. Signed-off-by:
Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Balaji T K authored
Mux mode for wlan/sdmmc5 should be MODE0 in pinmux_wl12xx_pins and Enable Pull up on sdmmc5_clk to detect SDIO card. This fixes WLAN on omap4-sdp that got broken in v3.10 when we moved omap4 to boot using device tree only as I did not have the WL12XX card in my omap4 SDP to test with. The commit that attempted to make WL12XX working on omap4 SDP was 775d2418 (ARM: dts: Fix muxing and regulator for wl12xx on the SDIO bus for blaze). Signed-off-by:
Balaji T K <balajitk@ti.com> [tony@atomide.com: updated comments for the regression] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Balaji T K authored
pin mux wl12xx_gpio and wl12xx_pins should be part of omap4_pmx_core and not omap4_pmx_wkup. So, move wl12xx_* to omap4_pmx_core. Fix the following error message: pinctrl-single 4a31e040.pinmux: mux offset out of range: 0x38 (0x38) pinctrl-single 4a31e040.pinmux: could not add functions for pinmux_wl12xx_pins 56x SDIO card is not detected after moving pin mux to omap4_pmx_core since sdmmc5_clk pull is disabled. Enable Pull up on sdmmc5_clk to detect SDIO card. This fixes a regression where WLAN did not work after a warm reset or after one up/down cycle that happened when we move omap4 to boot using device tree only. For reference, the kernel bug is described at: https://bugzilla.kernel.org/show_bug.cgi?id=63821 Cc: stable@vger.kernel.org # v3.10+ Signed-off-by:
Balaji T K <balajitk@ti.com> [tony@atomide.com: update comments to describe the regression] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Dec 02, 2013
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Nicolas Ferre authored
Alias was missing for SoC of the at91sam9x5 familly that embed USART3. Reported-by:
Jiri Prchal <jiri.prchal@aksignal.cz> [b.brezillon@overkiz.com: advised to place changes in at91sam9x5_usart3.dtsi] Acked-by:
Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Nov 27, 2013
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Roger Quadros authored
Beagle (rev. C4) and Beagle-XM (all revs) need VAUX2 1.8V supply for the USB PHY. As the generic PHY driver can't handle more than one supply at the moment, we configure this supply to be always on. This will cause a very small power impact if the USB host subsystem is not in use, about 76.86 micro-W + LDO power. Older Beagle boards (prior to C4) don't have VAUX2 connected anywhere, so there won't be any functional impact on those boards other than some additional LDO power consumption. Reported-by:
Nishanth Menon <nm@ti.com> Tested-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Javier Martinez Canillas authored
On Device Tree boot the VDDS_DSI regulator is not linked to the DPI device so omapfb driver probing fails with: [ 3.186035] OMAPFB: omapfb_probe [ 3.190704] omapdss DPI error: can't get VDDS_DSI regulator [ 3.196594] omapfb omapfb: failed to connect default display [ 3.202667] omapfb omapfb: failed to init overlay connections [ 3.208892] OMAPFB: free_resources [ 3.212493] OMAPFB: free all fbmem [ 3.216735] omapfb omapfb: failed to setup omapfb As a workaround name the VPLL2 regulator from twl4030 as vdds_dsi so getting the VDDS_DSI regulator will succeed on dpi_init_regulator(). Signed-off-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
Add node to support the USB Host and the USB OTG on the IGEP AQUILA Processor Board. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
The IGEP AQUILA EXPANSION has a 32KBit EEPROM for user data storage. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
Enable the user leds on the IGEP AQUILA EXPANSION. The has two leds, one green and one red, that are controllable by software. Signed-off-by:
Enric Balletbo i Serra <eballetbo@iseebcn.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
Enable the hdmi output and the LCD Controller on IGEP AQUILA. Also configure the correct pinmux for output of video data from the SoC to the HDMI encoder. Signed-off-by:
Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Javier Martinez Canillas authored
The IGEPv2 has a TFP410 DPI-to-DVI encoder attached to OMAP's Display SubSystem (DSS). Add mux setup for DSS pins and also for the GPIO 170 pin that is used to ensure that the DVI-D is powered down on power up. Signed-off-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Javier Martinez Canillas authored
Add pin muxing support for IGEP boards i2c controllers. Signed-off-by:
Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
Most of the boards are using the TI AM/DM37x processor, there is only a small quantity of IGEP Processor Boards based on TI OMAP3530. So it's better use the omap36xx.dtsi include instead of omap34xx.dtsi include. We can add support for the 34xx based variant later on as needed. To avoid confusion we have added to the model the (TI AM/DM37x) comment. Signed-off-by:
Enric Balletbo i Serra <eballetbo@gmail.com> [tony@atomide.com: updated comments for the 34xx to 36xx include change] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
The LBEE1USJYC is a WiFi/BT combo module used on OMAP3-based IGEP boards. In both cases, IGEPv2 Rev. C and IGEP COM MODULE, the module is connected using the same MMC interface and uses the same GPIOs. Signed-off-by:
Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Enric Balletbo i Serra authored
Both, IGEPv2 and IGEP COM MODULE have a bus-width of 4 not 8, so fix this and do not mux data pins from mmc1_data4 to mmc1_data7. Signed-off-by:
Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Nov 26, 2013
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Stephen Warren authored
The I2C controller node needs #address-cells and #size-cells properties, but these are currently missing. Add them. This allows child nodes to be parsed correctly. Cc: stable@vger.kernel.org Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Doug Anderson authored
Without the interrupt you'll get problems if you enable CONFIG_RTC_DRV_MAX77686. Setup the interrupt properly in the device tree. Signed-off-by:
Doug Anderson <dianders@chromium.org> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Signed-off-by:
Olof Johansson <olof@lixom.net> Cc: stable@vger.kernel.org
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Tony Lindgren authored
Looks like we need to configure the regulators and use the pdata quirk to make eMMC work with device tree. It seems that mostly vaux3 is used, and only some earlier revisions used vmmc2. This has been tested to work on devices where the system_rev passed by the bootloader has versions 0x0010, 0x2101 and 0x2204. Cc: devicetree@vger.kernel.org Cc: Pavel Machek <pavel@ucw.cz> Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
Sebastian Reichel <sre@debian.org> [tony@atomide.com: updated with pinctrl changes and comments from Sebastian] Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
After dropping the duplicate data in hwmod that now should come from the .dts files, I noticed few more entries missing. Let's add these as otherwise devices relying on these won't work. Looks like the side tone entries are bundled into the mcbsp1 to 3, so that may needs some special handling in the hwmod code as it's currently trying to look up mcbsp2_sidetone and mcbsp3_sidetone entries. Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Thomas Petazzoni authored
Commit 14fd8ed0 ("ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes") relocated the PCIe controller DT nodes one level up in the Device Tree, to reflect a more correct representation of the hardware introduced by the mvebu-mbus Device Tree binding. However, while most of the boards were properly adjusted accordingly, the Armada 370 DB board was left unchanged, and therefore, PCIe is seen as not enabled on this board. This patch fixes that by moving the PCIe controller node one level-up in armada-370-db.dts. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.12+ Fixes: 14fd8ed0 "ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes" Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Gregory CLEMENT authored
The Armada XP provides a mechanism called "virtual CPU registers" or "per-CPU register banking", to access the per-CPU registers of the current CPU, without having to worry about finding on which CPU we're running. CPU0 has its registers at 0x21800, CPU1 at 0x21900, CPU2 at 0x21A00 and CPU3 at 0x21B00. The virtual registers accessing the current CPU registers are at 0x21000. However, in the Device Tree node that provides the register addresses for the coherency unit (which is responsible for ensuring coherency between processors, and I/O coherency between processors and the DMA-capable devices), a mistake was made: the CPU0-specific registers were specified instead of the virtual CPU registers. This means that the coherency barrier needed for I/O coherency was not behaving properly when executed from a CPU different from CPU0. This patch fixes that by using the virtual CPU registers. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.8+ Fixes: e60304f8 "arm: mvebu: Add hardware I/O Coherency support" Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Nov 23, 2013
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Arnaud Ebalard authored
mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The two first units are both x4 and quad x1 capable. The third unit is only x4 capable. This patch fixes mv78260 .dtsi to reflect those capabilities. Signed-off-by:
Arnaud Ebalard <arno@natisbad.org> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.10.x Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Arnaud Ebalard authored
Various Marvell datasheets advertise second PCIe unit of mv78230 flavour of Armada XP as x4/quad x1 capable. This second unit is in fact only x1 capable. This patch fixes current mv78230 .dtsi to reflect that, i.e. makes 1.0 the second interface (instead of 2.0 at the moment). This was successfully tested on a mv78230-based ReadyNAS 2120 platform with a x1 device (FL1009 XHCI controller) connected to this second interface. Signed-off-by:
Arnaud Ebalard <arno@natisbad.org> Acked-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.10.x Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Nov 18, 2013
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Shawn Guo authored
The spdif "rxtx5" clock option is being set to ipg clk (62) by mistake. This causes an incorrect time keeping when spdif driver is running, because ipg is ancestor clock for clocksource while spdif driver will change the rate of this clock in certain circumstance. Before the correct clock for "rxtx5" option can be supplied, let's disable this option for now by filling a dummy clock for it. Reported-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- Nov 16, 2013
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Tony Lindgren authored
Looks like we're missing few entries for omap2 and the drivers have only worked because of the omap hwmod building the devices for the missing entries. Let's fix the missing entries so we don't need to rely on hwmod for the basic data and can then later on remove the duplicate data from hwmod. Otherwise device tree only drivers will not work properly. Cc: "Benoît Cousson" <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
Commit f2bf0e72 (ARM: OMAP2+: Add minimal 8250 support for GPMC) added support for using bootloader timings for some devices. Turns out we can do the same by looking at the compatible flags of the child without adding a new function as smc91x has a similar issue as 8250 with the bootloader timings. And let's fix the 8250 naming, we should use the device type as the name like uart instead of 8250 for zoom dts file. Cc: "Benoît Cousson" <bcousson@baylibre.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Nov 13, 2013
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NeilBrown authored
This allows the charger to be enabled with devicetree, and allows the parameters for charging the backup battery to be set. Signed-off-by:
NeilBrown <neilb@suse.de> Acked-by:
Kumar Gala <galak@codeaurora.org> Acked-by:
Grant Likely <grant.likely@linaro.org> Signed-off-by:
Anton Vorontsov <anton@enomsg.org>
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- Nov 11, 2013
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Alexander Shiyan authored
Proper clock ID for USB OTG PHY is "usb_phy_gate". The patch changes this mismatch. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Felipe Balbi authored
Add missing nodes for the touchscreen available on AM335x EVM SK. Signed-off-by:
Felipe Balbi <balbi@ti.com> Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com>
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Felipe Balbi authored
There was a spelling mistake on TSC/ADC binding where "coordinate" was spelled as "coordiante". We can't simply fix the error due to DT being an ABI, the approach taken was to first use correct spelling and if that fails, fall back to miss-spelled version. It's unfortunate that has creeped into the tree. Signed-off-by:
Felipe Balbi <balbi@ti.com> Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com>
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- Nov 05, 2013
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Rob Herring authored
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by:
Rob Herring <rob.herring@calxeda.com> [Device Tree documentation updated.] Signed-off-by:
Robert Richter <rric@kernel.org>
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- Nov 04, 2013
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Grant Likely authored
Commit 23616132 , "of/irq: Refactor interrupt-map parsing" introduced a bug. The irq parsing will fail for some nodes that don't have a reg property. It is fixed by deferring the check for reg until it is actually needed. Also adjust the testcase data to catch the bug. Signed-off-by:
Grant Likely <grant.likely@linaro.org> Tested-by:
Stephen Warren <swarren@nvidia.com> Tested-by:
Ming Lei <tom.leiming@gmail.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Cc: Rob Herring <rob.herring@calxeda.com>
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- Nov 01, 2013
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Matt Porter authored
Trivial patch to make use of GIC/IRQ defines on the bcm11351 sdio interrupt properties. Signed-off-by:
Matt Porter <matt.porter@linaro.org> Signed-off-by:
Christian Daudt <bcm@fixthebug.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Tim Kryger authored
This adds in three more UARTs that were not declared earlier. Signed-off-by:
Tim Kryger <tim.kryger@linaro.org> Reviewed-by:
Markus Mayer <markus.mayer@linaro.org> Reviewed-by:
Matt Porter <matt.porter@linaro.org> Signed-off-by:
Christian Daudt <bcm@fixthebug.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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