- May 10, 2016
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Arnd Bergmann authored
Merge tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late Merge "The i.MX device tree updates with new clocks for 4.7" from Shawn Guo: - Add LCDIF and FlexCAN device support for i.MX7D - New support i.MX7D based Nitrogen7 board from Boundary Devices - Add display support for vf610-colibri board * tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: vf610-colibri: enable display controller ARM: dts: vf610: add display nodes ARM: dts: imx: add Boundary Devices Nitrogen7 board ARM: dts: imx7d: add flexcan support ARM: dts: imx7d: add lcdif support clk: imx: vf610: fix whitespace in vf610-clock.h clk: imx: vf610: add TCON ipg clock clk: imx: vf610: fix DCU clock tree clk: imx: add ckil clock for i.MX7 clk: imx: vf610: add suspend/resume support clk: imx: vf610: add WKPU unit clk: imx: vf610: leave DDR clock on clk: imx: clk-gate2: allow custom gate configuration clk: imx6sx: Register SAI clocks as shared clocks
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- May 09, 2016
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Arnd Bergmann authored
Merge tag 'tegra-for-4.7-xusb-no-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late Merge "ARM: tegra: Enable the XUSB controller" from Thierry Reding: These changes add support for the XUSB controller on Tegra124. It is an XHCI compatible controller that replaces the existing EHCI controllers. Support is enabled on Venice2, Jetson TK1 and Nyan-based Chromebooks. * tag 'tegra-for-4.7-xusb-no-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding
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Arnd Bergmann authored
This is a prerequisite for enabling the Tegra XUSB, all the branches should be merged already at the time we get here. * tegra/pci: PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs * tegra/usb: usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
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Arnd Bergmann authored
Merge tag 'renesas-arm64-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Merge "Renesas ARM64 Based SoC DT PM Domain Updates for v4.7" from Simon Horman: * Add SYSC PM Domains to DT of r8a7795 SoC * tag 'renesas-arm64-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: r8a7795: Use SYSC "always-on" PM Domain arm64: dts: r8a7795: Add SYSC PM Domains arm64: dts: r8a7795: Don't disable referenced optional clocks arm64: dts: salvator-x: populate EXTALR arm64: dts: r8a7795: enable PCIe on Salvator-X arm64: dts: r8a7795: Add PCIe nodes arm64: dts: r8a7795: Use USB3.0 fallback compatibility string arm64: dts: r8a7795: Add CAN support arm64: dts: r8a7795: Add CAN external clock support
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- Apr 29, 2016
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Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Nyan boards. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Jetson TK1 board. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Venice2 board. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Use the new XUSB pad controller binding on Tegra124. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
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Thierry Reding authored
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Thierry Reding authored
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Thierry Reding authored
Parameterize more parts of the driver and add support for Tegra210. Acked-by:
Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add support for the on-chip XUSB controller present on Tegra SoCs. This controller, when loaded with external firmware, exposes an interface compliant with xHCI. This driver loads the firmware, starts the controller, and is able to service host-specific messages sent by the controller's firmware. The controller also supports USB device mode as well as powergating of the SuperSpeed and host-controller logic when not in use, but support for these is not yet implemented. Based on work by: Ajay Gupta <ajayg@nvidia.com> Bharath Yadav <byadav@nvidia.com> Andrew Bresticker <abrestic@chromium.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Extend the Tegra XUSB controller device tree binding with Tegra210 support. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add device-tree binding documentation for the XUSB controller present on Tegra124 and later SoCs. This controller supports USB 3.0 via an xHCI compliant interface. Based on work by Andrew Bresticker <abrestic@chromium.org>. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
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Thierry Reding authored
The current XUSB pad controller bindings are insufficient to describe PHY devices attached to USB controllers. New bindings have been created to overcome these restrictions. As a side-effect each root port now is assigned a set of PHY devices, one for each lane associated with the root port. This has the benefit of allowing fine-grained control of the power management for each lane. Acked-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The XUSB pad controller allows PCIe lanes to be controlled individually, providing fine-grained control over their power state. Previous attempts at describing the XUSB pad controller in DT had erroneously assumed that all PCIe lanes were driven by the same PHY, and hence the PCI host controller would reference only a single PHY. Moving to a representation of per-lane PHYs requires that the operating system driver for the PCI host controller have access to the set of PHY devices that make up the connection of each root port in order to power up and down all of the lanes as necessary. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
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Thierry Reding authored
Add support for the XUSB pad controller found on Tegra210 SoCs. The hardware is roughly the same, but some of the registers have been moved around and the number and type of supported pads has changed. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add a new driver for the XUSB pad controller found on NVIDIA Tegra SoCs. This hardware block used to be exposed as a pin controller, but it turns out that this isn't a good fit. The new driver and DT binding much more accurately describe the hardware and are more flexible in supporting new SoC generations. Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Extend the binding to cover the set of feature found in Tegra210. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a set of lanes that are used for PCIe, SATA and USB. A binding exists for the XUSB pad controller already, but it turned out not to be flexible enough to describe all aspects of the controller. In particular, the addition of XUSB support (for SuperSpeed USB) has shown that the existing binding is no longer suitable. Mark the old binding as deprecated and link to the new binding. Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
In order to more flexibly support device tree bindings, allow drivers to override the container of the child nodes. By default the device node of the PHY provider is assumed to be the parent for children, but bindings may decide to add additional levels for better organization. Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Apr 28, 2016
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Arnd Bergmann authored
Merge tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late Merge "Renesas ARM Based SoC DT PM Domain Updates for v4.7" into next/late * Add SYSC PM Domains to DT for R-Car Gen 1 and 2 SoCs This pull requests is based on a merge of: * "[GIT PULL] Second Round of Renesas ARM Based SoC R-Car SYSC Updates for v4.7", tagged as renesas-rcar-sysc2-for-v4.7, which you have already pulled. * "[GIT PULL v2] Renesas ARM Based SoC DT Updates for v4.7", tagged as renesas-dt-for-v4.7, which you have also already pulled. The reason for the somewhat tedious base on renesas-rcar-sysc2-for-v4.7, which provides driver changes, is a hard run-time dependency. I also have a similar set of changes for arm64 which I will send separately. * tag 'renesas-dt-pm-domain-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits) ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ARM: dts: r8a7791: Use SYSC "always-on" PM Domain ARM: dts: r8a7790: Use SYSC "always-on" PM Domain ARM: dts: r8a7779: Use SYSC "always-on" PM Domain ARM: dts: r8a7794: Add SYSC PM Domains ARM: dts: r8a7793: Add SYSC PM Domains ARM: dts: r8a7791: Add SYSC PM Domains ARM: dts: r8a7790: Add SYSC PM Domains ARM: dts: r8a7779: Add SYSC PM Domains soc: renesas: rcar-sysc: Add support for R-Car H3 power areas soc: renesas: rcar-sysc: Add support for R-Car E2 power areas soc: renesas: rcar-sysc: Add support for R-Car M2-N power areas soc: renesas: rcar-sysc: Add support for R-Car M2-W power areas soc: renesas: rcar-sysc: Add support for R-Car H2 power areas soc: renesas: rcar-sysc: Add support for R-Car H1 power areas soc: renesas: rcar-sysc: Enable Clock Domain for I/O devices ARM: dts: gose: Enable SDHI controllers ARM: dts: r8a7793: Add SDHI controllers ARM: dts: r8a7790: fix max-frequency for SDHI ...
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Thierry Reding authored
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Andrew Bresticker authored
On Tegra210, hardware control of the SATA and XUSB pad PLLs must be done during the UPHY enable sequence rather than the PLLE enable sequence. Export functions to do this so that hardware control can be enabled from the XUSB padctl driver. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Signed-off-by:
Rhyland Klein <rklein@nvidia.com> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Apr 27, 2016
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSTP Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up the Cortex-A7 CPU cores and the Cortex-A7 L2 cache/SCU to their respective PM Domains. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to their respective PM Domains. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up the Cortex-A15 CPU cores and the Cortex-A15 L2 cache/SCU to their respective PM Domains. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up the Cortex-A15 and Cortex-A7 CPU cores and L2 caches/SCUs to their respective PM Domains. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up ARM CPU cores 1-3 to their respective PM Domains. Note that ARM CPU core 0 cannot be shut off. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Hook up all devices that are part of the CPG/MSSR Clock Domain to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the System Controller. Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2 caches/SCUs to their respective PM Domains. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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