Newer
Older
<&cru SCLK_UPHY1_TCPDPHY_REF>;
};
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pd_vo@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
pd_vopb@RK3399_PD_VOPB {
reg = <RK3399_PD_VOPB>;
clocks = <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>;
pm_qos = <&qos_vop_big_r>,
<&qos_vop_big_w>;
};
pd_vopl@RK3399_PD_VOPL {
reg = <RK3399_PD_VOPL>;
clocks = <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
pm_qos = <&qos_vop_little>;
};
};
};
};
};
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
pmu_io_domains: io-domains {
compatible = "rockchip,rk3399-pmu-io-voltage-domain";
status = "disabled";
};
};
spi3: spi@ff350000 {
compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff350000 0x0 0x1000>;
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart4: serial@ff370000 {
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
reg = <0x0 0xff370000 0x0 0x100>;
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "disabled";
};
i2c0: i2c@ff3c0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3c0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@ff3d0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3d0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c8: i2c@ff3e0000 {
compatible = "rockchip,rk3399-i2c";
reg = <0x0 0xff3e0000 0x0 0x1000>;
assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
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};
pwm0: pwm@ff420000 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420000 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm1: pwm@ff420010 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420010 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm2: pwm@ff420020 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420020 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
pwm3: pwm@ff420030 {
compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff420030 0x0 0x10>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3a_pin>;
clocks = <&pmucru PCLK_RKPWM_PMU>;
clock-names = "pwm";
status = "disabled";
};
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE1024NS>;
clock-names = "pclk_efuse";
/* Data cells */
cpu_id: cpu-id@7 {
reg = <0x07 0x10>;
};
cpub_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
gpu_leakage: gpu-leakage@18 {
reg = <0x18 0x1>;
};
center_leakage: center-leakage@19 {
reg = <0x19 0x1>;
};
cpul_leakage: cpu-leakage@1a {
reg = <0x1a 0x1>;
};
logic_leakage: logic-leakage@1b {
reg = <0x1b 0x1>;
};
wafer_info: wafer-info@1c {
reg = <0x1c 0x1>;
};
};
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
rockchip,grf = <&pmugrf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&pmucru PLL_PPLL>;
assigned-clock-rates = <676000000>;
};
cru: clock-controller@ff760000 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
assigned-clock-rates =
<594000000>, <800000000>,
<1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>, <600000000>,
<100000000>, <50000000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk3399-io-voltage-domain";
status = "disabled";
};
u2phy0: usb2-phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "clk_usbphy0_480m";
status = "disabled";
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
status = "disabled";
};
u2phy0_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@e460 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe460 0x10>;
clocks = <&cru SCLK_USB2PHY1_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "clk_usbphy1_480m";
status = "disabled";
u2phy1_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
status = "disabled";
};
u2phy1_otg: otg-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id",
"linestate";
status = "disabled";
};
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
clocks = <&sdhci>;
clock-names = "emmcclk";
#phy-cells = <0>;
status = "disabled";
};
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <0>;
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
status = "disabled";
};
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD0>;
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resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
rockchip,typec-conn-dir = <0xe580 0 16>;
rockchip,usb3tousb2-en = <0xe580 3 19>;
rockchip,external-psm = <0xe588 14 30>;
rockchip,pipe-status = <0xe5c0 0 0>;
status = "disabled";
tcphy0_dp: dp-port {
#phy-cells = <0>;
};
tcphy0_usb3: usb3-port {
#phy-cells = <0>;
};
};
tcphy1: phy@ff800000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff800000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
assigned-clock-rates = <50000000>;
power-domains = <&power RK3399_PD_TCPD1>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
rockchip,typec-conn-dir = <0xe58c 0 16>;
rockchip,usb3tousb2-en = <0xe58c 3 19>;
rockchip,external-psm = <0xe594 14 30>;
rockchip,pipe-status = <0xe5c0 16 16>;
status = "disabled";
tcphy1_dp: dp-port {
#phy-cells = <0>;
};
tcphy1_usb3: usb3-port {
#phy-cells = <0>;
};
};
watchdog@ff848000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
rktimer: rktimer@ff850000 {
compatible = "rockchip,rk3399-timer";
reg = <0x0 0xff850000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
clock-names = "pclk", "timer";
};
spdif: spdif@ff870000 {
compatible = "rockchip,rk3399-spdif";
reg = <0x0 0xff870000 0x0 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 7>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_bus>;
status = "disabled";
};
i2s0: i2s@ff880000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff880000 0x0 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_8ch_bus>;
status = "disabled";
};
i2s1: i2s@ff890000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
pinctrl-names = "default";
pinctrl-0 = <&i2s1_2ch_bus>;
status = "disabled";
};
i2s2: i2s@ff8a0000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff8a0000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio0@ff720000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio1: gpio1@ff730000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio2: gpio2@ff780000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio3: gpio3@ff788000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
gpio4: gpio4@ff790000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
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gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
bias-disable;
drive-strength = <12>;
};
pcfg_pull_up_8ma: pcfg-pull-up-8ma {
bias-pull-up;
drive-strength = <8>;
};
pcfg_pull_down_4ma: pcfg-pull-down-4ma {
bias-pull-down;
drive-strength = <4>;
};
pcfg_pull_up_2ma: pcfg-pull-up-2ma {
bias-pull-up;
drive-strength = <2>;
};
pcfg_pull_down_12ma: pcfg-pull-down-12ma {
bias-pull-down;
drive-strength = <12>;
};
pcfg_pull_none_13ma: pcfg-pull-none-13ma {
bias-disable;
drive-strength = <13>;
};
clock {
clk_32k: clk-32k {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
};
};
edp {
edp_hpd: edp-hpd {
rockchip,pins =
<4 23 RK_FUNC_2 &pcfg_pull_none>;
};
};
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gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
/* mac_txclk */
<3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxclk */
<3 14 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<3 8 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxd3 */
<3 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd2 */
<3 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
<3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd2 */
<3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
rmii_pins: rmii-pins {
rockchip,pins =
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
<3 10 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<3 8 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
};
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i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
<1 15 RK_FUNC_2 &pcfg_pull_none>,
<1 16 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins =
<4 2 RK_FUNC_1 &pcfg_pull_none>,
<4 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins =
<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins =
<4 17 RK_FUNC_1 &pcfg_pull_none>,
<4 16 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins =
<1 12 RK_FUNC_1 &pcfg_pull_none>,
<1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins =
<3 11 RK_FUNC_2 &pcfg_pull_none>,
<3 10 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c6 {
i2c6_xfer: i2c6-xfer {
rockchip,pins =
<2 10 RK_FUNC_2 &pcfg_pull_none>,
<2 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c7 {
i2c7_xfer: i2c7-xfer {
rockchip,pins =
<2 8 RK_FUNC_2 &pcfg_pull_none>,
<2 7 RK_FUNC_2 &pcfg_pull_none>;
};
};
i2c8 {
i2c8_xfer: i2c8-xfer {
rockchip,pins =
<1 21 RK_FUNC_1 &pcfg_pull_none>,
<1 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_8ch_bus: i2s0-8ch-bus {
rockchip,pins =
<3 24 RK_FUNC_1 &pcfg_pull_none>,
<3 25 RK_FUNC_1 &pcfg_pull_none>,
<3 26 RK_FUNC_1 &pcfg_pull_none>,
<3 27 RK_FUNC_1 &pcfg_pull_none>,
<3 28 RK_FUNC_1 &pcfg_pull_none>,
<3 29 RK_FUNC_1 &pcfg_pull_none>,
<3 30 RK_FUNC_1 &pcfg_pull_none>,
<3 31 RK_FUNC_1 &pcfg_pull_none>,
<4 0 RK_FUNC_1 &pcfg_pull_none>;
};
};
i2s1 {
i2s1_2ch_bus: i2s1-2ch-bus {
rockchip,pins =
<4 3 RK_FUNC_1 &pcfg_pull_none>,
<4 4 RK_FUNC_1 &pcfg_pull_none>,
<4 5 RK_FUNC_1 &pcfg_pull_none>,
<4 6 RK_FUNC_1 &pcfg_pull_none>,
<4 7 RK_FUNC_1 &pcfg_pull_none>;
};
};
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sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins =
<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
rockchip,pins =
<2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>,
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>,
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>,
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins =
<2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
rockchip,pins =
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
rockchip,pins =
<2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
rockchip,pins =
<2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
rockchip,pins =
<2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
rockchip,pins =
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
rockchip,pins =
<0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>;
};
};
sdmmc {
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>,
<4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
<4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>,
<4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_cd: sdmcc-cd {
rockchip,pins =
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
};
sdmmc_wp: sdmmc-wp {
rockchip,pins =
<0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
};
};
sleep {
ap_pwroff: ap-pwroff {
rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
};
};
spdif {
spdif_bus: spdif-bus {
rockchip,pins =
<4 21 RK_FUNC_1 &pcfg_pull_none>;
};
spdif_bus_1: spdif-bus-1 {
rockchip,pins =
<3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>;
};
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};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
<3 6 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins =
<3 7 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins =
<3 8 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins =
<3 5 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins =
<3 4 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins =
<1 9 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins =
<1 10 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins =
<1 7 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins =
<1 8 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi2 {
spi2_clk: spi2-clk {
rockchip,pins =
<2 11 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins =
<2 12 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins =
<2 9 RK_FUNC_1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins =
<2 10 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi3 {
spi3_clk: spi3-clk {
rockchip,pins =
<1 17 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_cs0: spi3-cs0 {
rockchip,pins =
<1 18 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_rx: spi3-rx {
rockchip,pins =
<1 15 RK_FUNC_1 &pcfg_pull_up>;
};
spi3_tx: spi3-tx {
rockchip,pins =
<1 16 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi4 {
spi4_clk: spi4-clk {
rockchip,pins =
<3 2 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_cs0: spi4-cs0 {
rockchip,pins =
<3 3 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_rx: spi4-rx {
rockchip,pins =
<3 0 RK_FUNC_2 &pcfg_pull_up>;
};
spi4_tx: spi4-tx {
rockchip,pins =
<3 1 RK_FUNC_2 &pcfg_pull_up>;
};
};
spi5 {
spi5_clk: spi5-clk {
rockchip,pins =
<2 22 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_cs0: spi5-cs0 {
rockchip,pins =
<2 23 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_rx: spi5-rx {
rockchip,pins =
<2 20 RK_FUNC_2 &pcfg_pull_up>;
};
spi5_tx: spi5-tx {
rockchip,pins =
<2 21 RK_FUNC_2 &pcfg_pull_up>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
};
};
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uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
<2 16 RK_FUNC_1 &pcfg_pull_up>,
<2 17 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
rockchip,pins =
<2 18 RK_FUNC_1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
rockchip,pins =
<2 19 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins =
<3 12 RK_FUNC_2 &pcfg_pull_up>,
<3 13 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2a {
uart2a_xfer: uart2a-xfer {
rockchip,pins =
<4 8 RK_FUNC_2 &pcfg_pull_up>,
<4 9 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2b {
uart2b_xfer: uart2b-xfer {
rockchip,pins =
<4 16 RK_FUNC_2 &pcfg_pull_up>,
<4 17 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart2c {
uart2c_xfer: uart2c-xfer {
rockchip,pins =
<4 19 RK_FUNC_1 &pcfg_pull_up>,
<4 20 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart3 {
uart3_xfer: uart3-xfer {