rk3399.dtsi

		#size-cells = <1>;
		clocks = <&cru PCLK_EFUSE1024NS>;
		clock-names = "pclk_efuse";

		/* Data cells */
		cpub_leakage: cpu-leakage@17 {
			reg = <0x17 0x1>;
		};
		gpu_leakage: gpu-leakage@18 {
			reg = <0x18 0x1>;
		};
		center_leakage: center-leakage@19 {
			reg = <0x19 0x1>;
		};
		cpul_leakage: cpu-leakage@1a {
			reg = <0x1a 0x1>;
		};
		logic_leakage: logic-leakage@1b {
			reg = <0x1b 0x1>;
		};
		wafer_info: wafer-info@1c {
			reg = <0x1c 0x1>;
		};
	};

	pmucru: pmu-clock-controller@ff750000 {
		compatible = "rockchip,rk3399-pmucru";
		reg = <0x0 0xff750000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&pmucru PLL_PPLL>;
		assigned-clock-rates = <676000000>;
	};

	cru: clock-controller@ff760000 {
		compatible = "rockchip,rk3399-cru";
		reg = <0x0 0xff760000 0x0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks =
			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
			<&cru PLL_NPLL>,
			<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
			<&cru PCLK_PERIHP>,
			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
		assigned-clock-rates =
			 <594000000>,  <800000000>,
			<1000000000>,
			 <150000000>,   <75000000>,
			  <37500000>,
			 <100000000>,  <100000000>,
			  <50000000>, <600000000>,
			 <100000000>,   <50000000>;
	};

	grf: syscon@ff770000 {
		compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
		reg = <0x0 0xff770000 0x0 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;

		io_domains: io-domains {
			compatible = "rockchip,rk3399-io-voltage-domain";
			status = "disabled";
		};

		u2phy0: usb2-phy@e450 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe450 0x10>;
			clocks = <&cru SCLK_USB2PHY0_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "clk_usbphy0_480m";
			status = "disabled";

			u2phy0_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
			};
		};

		u2phy1: usb2-phy@e460 {
			compatible = "rockchip,rk3399-usb2phy";
			reg = <0xe460 0x10>;
			clocks = <&cru SCLK_USB2PHY1_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			clock-output-names = "clk_usbphy1_480m";
			status = "disabled";

			u2phy1_host: host-port {
				#phy-cells = <0>;
				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
				interrupt-names = "linestate";
				status = "disabled";
			};
		};

		emmc_phy: phy@f780 {
			compatible = "rockchip,rk3399-emmc-phy";
			reg = <0xf780 0x24>;
			clocks = <&sdhci>;
			clock-names = "emmcclk";
			#phy-cells = <0>;
			status = "disabled";
		};

		pcie_phy: pcie-phy {
			compatible = "rockchip,rk3399-pcie-phy";
			clocks = <&cru SCLK_PCIEPHY_REF>;
			clock-names = "refclk";
			#phy-cells = <0>;
			resets = <&cru SRST_PCIEPHY>;
			reset-names = "phy";
			status = "disabled";
		};
	};

	watchdog@ff848000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0xff848000 0x0 0x100>;
		clocks = <&cru PCLK_WDT>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
	};

	rktimer: rktimer@ff850000 {
		compatible = "rockchip,rk3399-timer";
		reg = <0x0 0xff850000 0x0 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
		clock-names = "pclk", "timer";
	};

	spdif: spdif@ff870000 {
		compatible = "rockchip,rk3399-spdif";
		reg = <0x0 0xff870000 0x0 0x1000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 7>;
		dma-names = "tx";
		clock-names = "mclk", "hclk";
		clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
		pinctrl-names = "default";
		pinctrl-0 = <&spdif_bus>;
		status = "disabled";
	};

	i2s0: i2s@ff880000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff880000 0x0 0x1000>;
		rockchip,grf = <&grf>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 0>, <&dmac_bus 1>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_8ch_bus>;
		status = "disabled";
	};

	i2s1: i2s@ff890000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff890000 0x0 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 2>, <&dmac_bus 3>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_2ch_bus>;
		status = "disabled";
	};

	i2s2: i2s@ff8a0000 {
		compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff8a0000 0x0 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
		dmas = <&dmac_bus 4>, <&dmac_bus 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
		status = "disabled";
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3399-pinctrl";
		rockchip,grf = <&grf>;
		rockchip,pmu = <&pmugrf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio0@ff720000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff720000 0x0 0x100>;
			clocks = <&pmucru PCLK_GPIO0_PMU>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio1: gpio1@ff730000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff730000 0x0 0x100>;
			clocks = <&pmucru PCLK_GPIO1_PMU>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio2: gpio2@ff780000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff780000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO2>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio3: gpio3@ff788000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff788000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO3>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		gpio4: gpio4@ff790000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff790000 0x0 0x100>;
			clocks = <&cru PCLK_GPIO4>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;

			gpio-controller;
			#gpio-cells = <0x2>;

			interrupt-controller;
			#interrupt-cells = <0x2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <12>;
		};

		pcfg_pull_up_8ma: pcfg-pull-up-8ma {
			bias-pull-up;
			drive-strength = <8>;
		};

		pcfg_pull_down_4ma: pcfg-pull-down-4ma {
			bias-pull-down;
			drive-strength = <4>;
		};

		pcfg_pull_up_2ma: pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <2>;
		};

		pcfg_pull_down_12ma: pcfg-pull-down-12ma {
			bias-pull-down;
			drive-strength = <12>;
		};

		pcfg_pull_none_13ma: pcfg-pull-none-13ma {
			bias-disable;
			drive-strength = <13>;
		};

		clock {
			clk_32k: clk-32k {
				rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins =
					<1 15 RK_FUNC_2 &pcfg_pull_none>,
					<1 16 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins =
					<4 2 RK_FUNC_1 &pcfg_pull_none>,
					<4 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins =
					<2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
					<2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins =
					<4 17 RK_FUNC_1 &pcfg_pull_none>,
					<4 16 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins =
					<1 12 RK_FUNC_1 &pcfg_pull_none>,
					<1 11 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c5 {
			i2c5_xfer: i2c5-xfer {
				rockchip,pins =
					<3 11 RK_FUNC_2 &pcfg_pull_none>,
					<3 10 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c6 {
			i2c6_xfer: i2c6-xfer {
				rockchip,pins =
					<2 10 RK_FUNC_2 &pcfg_pull_none>,
					<2 9 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c7 {
			i2c7_xfer: i2c7-xfer {
				rockchip,pins =
					<2 8 RK_FUNC_2 &pcfg_pull_none>,
					<2 7 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c8 {
			i2c8_xfer: i2c8-xfer {
				rockchip,pins =
					<1 21 RK_FUNC_1 &pcfg_pull_none>,
					<1 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s0 {
			i2s0_8ch_bus: i2s0-8ch-bus {
				rockchip,pins =
					<3 24 RK_FUNC_1 &pcfg_pull_none>,
					<3 25 RK_FUNC_1 &pcfg_pull_none>,
					<3 26 RK_FUNC_1 &pcfg_pull_none>,
					<3 27 RK_FUNC_1 &pcfg_pull_none>,
					<3 28 RK_FUNC_1 &pcfg_pull_none>,
					<3 29 RK_FUNC_1 &pcfg_pull_none>,
					<3 30 RK_FUNC_1 &pcfg_pull_none>,
					<3 31 RK_FUNC_1 &pcfg_pull_none>,
					<4 0 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s1 {
			i2s1_2ch_bus: i2s1-2ch-bus {
				rockchip,pins =
					<4 3 RK_FUNC_1 &pcfg_pull_none>,
					<4 4 RK_FUNC_1 &pcfg_pull_none>,
					<4 5 RK_FUNC_1 &pcfg_pull_none>,
					<4 6 RK_FUNC_1 &pcfg_pull_none>,
					<4 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		sleep {
			ap_pwroff: ap-pwroff {
				rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
			};

			ddrio_pwroff: ddrio-pwroff {
				rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spdif {
			spdif_bus: spdif-bus {
				rockchip,pins =
					<4 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins =
					<3 6 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins =
					<3 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins =
					<3 8 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins =
					<3 5 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins =
					<3 4 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins =
					<1 9 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins =
					<1 10 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins =
					<1 7 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins =
					<1 8 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		spi2 {
			spi2_clk: spi2-clk {
				rockchip,pins =
					<2 11 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi2_cs0: spi2-cs0 {
				rockchip,pins =
					<2 12 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi2_rx: spi2-rx {
				rockchip,pins =
					<2 9 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi2_tx: spi2-tx {
				rockchip,pins =
					<2 10 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi3 {
			spi3_clk: spi3-clk {
				rockchip,pins =
					<1 17 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi3_cs0: spi3-cs0 {
				rockchip,pins =
					<1 18 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi3_rx: spi3-rx {
				rockchip,pins =
					<1 15 RK_FUNC_1 &pcfg_pull_up>;
			};
			spi3_tx: spi3-tx {
				rockchip,pins =
					<1 16 RK_FUNC_1 &pcfg_pull_up>;
			};
		};

		spi4 {
			spi4_clk: spi4-clk {
				rockchip,pins =
					<3 2 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi4_cs0: spi4-cs0 {
				rockchip,pins =
					<3 3 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi4_rx: spi4-rx {
				rockchip,pins =
					<3 0 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi4_tx: spi4-tx {
				rockchip,pins =
					<3 1 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		spi5 {
			spi5_clk: spi5-clk {
				rockchip,pins =
					<2 22 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi5_cs0: spi5-cs0 {
				rockchip,pins =
					<2 23 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi5_rx: spi5-rx {
				rockchip,pins =
					<2 20 RK_FUNC_2 &pcfg_pull_up>;
			};
			spi5_tx: spi5-tx {
				rockchip,pins =
					<2 21 RK_FUNC_2 &pcfg_pull_up>;
			};
		};

		tsadc {
			otp_gpio: otp-gpio {
				rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
			};

			otp_out: otp-out {
				rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins =
					<2 16 RK_FUNC_1 &pcfg_pull_up>,
					<2 17 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins =
					<2 18 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins =
					<2 19 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins =
					<3 12 RK_FUNC_2 &pcfg_pull_up>,
					<3 13 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart2a {
			uart2a_xfer: uart2a-xfer {
				rockchip,pins =
					<4 8 RK_FUNC_2 &pcfg_pull_up>,
					<4 9 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart2b {
			uart2b_xfer: uart2b-xfer {
				rockchip,pins =
					<4 16 RK_FUNC_2 &pcfg_pull_up>,
					<4 17 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart2c {
			uart2c_xfer: uart2c-xfer {
				rockchip,pins =
					<4 19 RK_FUNC_1 &pcfg_pull_up>,
					<4 20 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins =
					<3 14 RK_FUNC_2 &pcfg_pull_up>,
					<3 15 RK_FUNC_2 &pcfg_pull_none>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins =
					<3 18 RK_FUNC_2 &pcfg_pull_none>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins =
					<3 19 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart4 {
			uart4_xfer: uart4-xfer {
				rockchip,pins =
					<1 7 RK_FUNC_1 &pcfg_pull_up>,
					<1 8 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uarthdcp {
			uarthdcp_xfer: uarthdcp-xfer {
				rockchip,pins =
					<4 21 RK_FUNC_2 &pcfg_pull_up>,
					<4 22 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins =
					<4 18 RK_FUNC_1 &pcfg_pull_none>;
			};

			vop0_pwm_pin: vop0-pwm-pin {
				rockchip,pins =
					<4 18 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins =
					<4 22 RK_FUNC_1 &pcfg_pull_none>;
			};

			vop1_pwm_pin: vop1-pwm-pin {
				rockchip,pins =
					<4 18 RK_FUNC_3 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins =
					<1 19 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3a {
			pwm3a_pin: pwm3a-pin {
				rockchip,pins =
					<0 6 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3b {
			pwm3b_pin: pwm3b-pin {
				rockchip,pins =
					<1 14 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pcie {
			pcie_clkreqn: pci-clkreqn {
				rockchip,pins =
					<2 26 RK_FUNC_2 &pcfg_pull_none>;
			};

			pcie_clkreqnb: pci-clkreqnb {
				rockchip,pins =
					<4 24 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

	};
};