!3689 Intel: Backport Sierra Forest(SRF) core PMU support to OLK-5.10

Merge Pull Request from: @yunyingsun 
 
Title:  Add core PMU support for Intel Sierra Forest(SRF)

Content:
This PR is backporting Intel Sierra Forest (SRF) core PMU support to OpenEuler kernel devel-5.10, so that end users can access the core PMU counters via perf on next Intel E-core Xeon server SRF.

Upstream commit(v6.6-rc1):
a430021f perf/x86/intel: Add Crestmont PMU

Since SRF is an E-core only server platform and it shares same Crestmont core with Meteor Lake, its core PMU enabling is based on hybrid PMU driver which was firstly introduced since Alder Lake and later evolved with Raptor Lake. There are lots of hybrid PMU related commits needed as dependencies.

Besides the upstream commit, totally there're 55 dependent patches identified and backported.
The complete commit list of dependent patches:

v6.6-rc1(3): //mem_attr = grt_mem_attrs;
53544562 x86/cpu: Update Hybrids
0cfd8fba x86/cpu: Fix Crestmont uarch
882cdb06 x86/cpu: Fix Gracemont uarch

v6.3-rc1(7): // x86_pmu.pebs_latency_data = mtl_latency_data_small;
b0bd3336 perf/x86/msr: Add Meteor Lake support
eaef048c perf/x86/cstate: Add Meteor Lake support
eb467aaa perf/x86/intel: Support Architectural PerfMon Extension leaf
a018d2e3 x86/cpufeatures: Add Architectural PerfMon Extension bit
c87a3109 perf/x86: Support Retire Latency
38aaf921 perf/x86: Add Meteor Lake support

v6.0 (3):
b6c00fb9 perf: Add PMU_FORMAT_ATTR_SHOW
24919fde perf/x86/intel: Fix unchecked MSR access error for Alder Lake N
5515d21c x86/cpu: Add CPU model numbers for Meteor Lake

v6.0-rc1(2):
ccf170e9 perf/x86/intel: Fix PEBS data source encoding for ADL
39a41278 perf/x86/intel: Fix PEBS memory access info encoding for ADL

v5.19-rc1(5) // case INTEL_FAM6_ALDERLAKE_N:
f758bc5a perf/x86/uncore: Add new Alder Lake and Raptor Lake support
e5ae168e perf/x86/uncore: Clean up uncore_pci_ids[]
cd971104 perf/x86/cstate: Add new Alder Lake and Raptor Lake support
d773a733 perf/x86/msr: Add new Alder Lake and Raptor Lake support
c2a960f7 perf/x86: Add new Alder Lake and Raptor Lake support

v5.18-rc5(1): // case INTEL_FAM6_ALDERLAKE_N:
3ccce934 x86/cpu: Add new Alderlake and Raptorlake CPU model numbers

v5.18-rc2(4): // case INTEL_FAM6_RAPTORLAKE:
ad4878d4 perf/x86/uncore: Add Raptor Lake uncore support
82cd8304 perf/x86/msr: Add Raptor Lake CPU support
2da202aa perf/x86/cstate: Add Raptor Lake support
c61759e5 perf/x86: Add Intel Raptor Lake support

5.17-rc2(2):
5a4487f9 perf/x86/intel/uncore: Add IMC uncore support for ADL
7fa981ca perf/x86/intel: Add a quirk for the calculation of the number of counters on Alder Lake

v5.16-rc4(1):
7d697f0d x86/cpu: Drop spurious underscore from RAPTOR_LAKE #define

v5.16-rc1(1):
fbdb5e8f x86/cpu: Add Raptor Lake to Intel family

v5.14-rc5(1):
acade637 perf/x86/intel: Apply mid ACK for small core

v5.14-rc1(1)
ee72a94e perf/x86/intel: Fix fixed counter check warning for some Alder Lake

5.13-rc1(24):
6a5f4386 perf/x86/rapl: Add support for Intel Alder Lake
d0ca946b perf/x86/cstate: Add Alder Lake CPU support
19d3a81f perf/x86/msr: Add Alder Lake CPU support
772ed05f perf/x86/intel/uncore: Add Alder Lake support
55bcf6ef perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
f83d2f91 perf/x86/intel: Add Alder Lake Hybrid support
3e9a8b21 perf/x86: Support filter_match callback
58ae30c2 perf/x86/intel: Add attr_update for Hybrid PMUs
a9c81ccd perf/x86: Add structures for the attributes of Hybrid PMUs
d9977c43 perf/x86: Register hybrid PMUs
e11c1a7e perf/x86: Factor out x86_pmu_show_pmu_cap
b9856729 perf/x86: Remove temporary pmu assignment in event_init
34d5b61f perf/x86/intel: Factor out intel_pmu_check_extra_regs
bc14fe1b perf/x86/intel: Factor out intel_pmu_check_event_constraints
b8c4d1a8 perf/x86/intel: Factor out intel_pmu_check_num_counters
183af736 perf/x86: Hybrid PMU support for extra_regs
24ee38ff perf/x86: Hybrid PMU support for event constraints
0d18f2df perf/x86: Hybrid PMU support for hardware cache event
eaacf07d perf/x86: Hybrid PMU support for unconstrained
d4b294bf perf/x86: Hybrid PMU support for counters
fc4b8fca perf/x86: Hybrid PMU support for intel_ctrl
d0946a88 perf/x86/intel: Hybrid PMU support for perf capabilities
250b3c0d x86/cpu: Add helper function to get the type of the current hybrid CPU
a161545a x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit

v5.11-rc1(1):
c2208046 perf/x86/intel: Add Tremont Topdown support

Some of the backported patches have slightly code deviations from its upstream version, mainly because upstream commit contains code or functions that OLK-5.10 not yet supported.

The backported patch set have been verified on Intel internal Sierra Forest SP system.

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/I8RWG5

Test:
Platform dependent core PMU events do not work on SRF without this PR, like "L1-dcache-loads":
`# perf stat -a -e L1-dcache-loads -- sleep 1

 Performance counter stats for 'system wide':

   <not supported>      L1-dcache-loads

       1.029285911 seconds time elapsed`

With this PR applied to kernel OLK-5.10, it works:
`# perf stat -a -e L1-dcache-loads -- sleep 1

 Performance counter stats for 'system wide':

         7,354,296      L1-dcache-loads

       1.030988869 seconds time elapsed`

Known issue:
N/A

Default config change:
N/A 
 
Link:https://gitee.com/openeuler/kernel/pulls/3689

 

Reviewed-by: Xu Kuohai <xukuohai@huawei.com>
Reviewed-by: Jason Zeng <jason.zeng@intel.com>
Reviewed-by: Aichun Shi <aichun.shi@intel.com>
Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com>