Commit 882cdb06 authored by Peter Zijlstra's avatar Peter Zijlstra
Browse files

x86/cpu: Fix Gracemont uarch 



Alderlake N is an E-core only product using Gracemont
micro-architecture. It fits the pre-existing naming scheme perfectly
fine, adhere to it.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: default avatarHans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20230807150405.686834933@infradead.org
parent 62af0322

arch/x86/events/intel/core.c

+1 −1
Original line number Diff line number Diff line
@@ -6167,7 +6167,7 @@ __init int intel_pmu_init(void) 
		name = "Tremont";

		break;



	case INTEL_FAM6_ALDERLAKE_N:

	case INTEL_FAM6_ATOM_GRACEMONT:

		x86_pmu.mid_ack = true;

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

arch/x86/events/intel/cstate.c

+1 −1
Original line number Diff line number Diff line
@@ -669,6 +669,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,	&glm_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&adl_cstates),



	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&icl_cstates),
@@ -684,7 +685,6 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&adl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,	&adl_cstates),

arch/x86/events/intel/uncore.c

+1 −1
Original line number Diff line number Diff line
@@ -1858,7 +1858,6 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,		&rkl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&adl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,	&adl_uncore_init),
@@ -1867,6 +1866,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&snr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&adl_uncore_init),

	{},

};

MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match);

arch/x86/events/msr.c

+1 −1
Original line number Diff line number Diff line
@@ -106,7 +106,7 @@ static bool test_intel(int idx, void *data) 
	case INTEL_FAM6_ROCKETLAKE:

	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_ALDERLAKE_N:

	case INTEL_FAM6_ATOM_GRACEMONT:

	case INTEL_FAM6_RAPTORLAKE:

	case INTEL_FAM6_RAPTORLAKE_P:

	case INTEL_FAM6_RAPTORLAKE_S:

arch/x86/events/rapl.c

+1 −1
Original line number Diff line number Diff line
@@ -804,7 +804,7 @@ static const struct x86_cpu_id rapl_model_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&model_spr),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&model_spr),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&model_skl),