Commit 0d18f2df authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86: Hybrid PMU support for hardware cache event 



The hardware cache events are different among hybrid PMUs. Each hybrid
PMU should have its own hw cache event table.

Suggested-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1618237865-33448-9-git-send-email-kan.liang@linux.intel.com
parent eaacf07d

arch/x86/events/core.c

+2 −3
Original line number Diff line number Diff line
@@ -376,8 +376,7 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) 
		return -EINVAL;

	cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);



	val = hw_cache_event_ids[cache_type][cache_op][cache_result];



	val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result];

	if (val == 0)

		return -ENOENT;
@@ -385,7 +384,7 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) 
		return -EINVAL;



	hwc->config |= val;

	attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];

	attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result];

	return x86_pmu_extra_regs(val, event);

}

arch/x86/events/perf_event.h

+9 −0
Original line number Diff line number Diff line
@@ -639,6 +639,15 @@ struct x86_hybrid_pmu { 
	int				num_counters;

	int				num_counters_fixed;

	struct event_constraint		unconstrained;



	u64				hw_cache_event_ids

					[PERF_COUNT_HW_CACHE_MAX]

					[PERF_COUNT_HW_CACHE_OP_MAX]

					[PERF_COUNT_HW_CACHE_RESULT_MAX];

	u64				hw_cache_extra_regs

					[PERF_COUNT_HW_CACHE_MAX]

					[PERF_COUNT_HW_CACHE_OP_MAX]

					[PERF_COUNT_HW_CACHE_RESULT_MAX];

};



static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)