Commit a64b79c0 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' into clk-next

 - Add resets for MediaTek MT8195 PCIe and USB
 - Remove DaVinci DM644x and DM646x clk driver support

* clk-samsung:
  clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
  clk: samsung: exynos850: Implement CMU_MFCMSCL domain
  clk: samsung: exynos850: Implement CMU_IS domain
  clk: samsung: exynos850: Implement CMU_AUD domain
  clk: samsung: exynos850: Style fixes
  clk: samsung: exynosautov9: add fsys1 clock support
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: correct register offsets of peric0/c1
  clk: samsung: exynosautov9: add missing gate clks for peric0/c1
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  clk: samsung: exynos7885: Add TREX clocks
  clk: samsung: exynos7885: Implement CMU_FSYS domain
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
  clk: samsung: exynos-clkout: Use of_device_get_match_data()

* clk-mtk: (42 commits)
  clk: mediatek: add driver for MT8365 SoC
  clk: mediatek: Export required common code symbols
  clk: mediatek: Provide mtk_devm_alloc_clk_data
  dt-bindings: clock: mediatek: add bindings for MT8365 SoC
  clk: mediatek: mt8192: deduplicate parent clock lists
  clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()
  clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup
  clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
  clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
  clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
  clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
  clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux
  clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
  clk: mediatek: mt8183: Add clk mux notifier for MFG mux
  clk: mediatek: mux: add clk notifier functions
  clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
  clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe
  clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
  clk: mediatek: add VDOSYS1 clock
  dt-bindings: clk: mediatek: Add MT8195 DPI clocks
  ...

* clk-rm:
  clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x

* clk-ast:
  clk: ast2600: BCLK comes from EPLL

* clk-qcom: (97 commits)
  clk: qcom: gcc-sm6375: Ensure unsigned long type
  clk: qcom: gcc-sm6375: Remove unused variables
  clk: qcom: kpss-xcc: convert to parent data API
  clk: introduce (devm_)hw_register_mux_parent_data_table API
  clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8939: use parent_hws where possible
  dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
  clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc8280xp: use retention for USB power domains
  clk: qcom: gdsc: add missing error handling
  dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos
  clk: qcom: Add global clock controller driver for SM6375
  dt-bindings: clock: add SM6375 QCOM global clock bindings
  clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit
  clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs
  clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc
  clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
  clk: qcom: Add SC8280XP GPU clock controller
  dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
  clk: qcom: smd: Add SM6375 clocks
  ...
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+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ properties:
              - mediatek,mt2701-infracfg
              - mediatek,mt2712-infracfg
              - mediatek,mt6765-infracfg
              - mediatek,mt6795-infracfg
              - mediatek,mt6779-infracfg_ao
              - mediatek,mt6797-infracfg
              - mediatek,mt7622-infracfg
@@ -60,6 +61,7 @@ if:
        enum:
          - mediatek,mt2701-infracfg
          - mediatek,mt2712-infracfg
          - mediatek,mt6795-infracfg
          - mediatek,mt7622-infracfg
          - mediatek,mt7986-infracfg
          - mediatek,mt8135-infracfg
+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties:
              - mediatek,mt2712-mmsys
              - mediatek,mt6765-mmsys
              - mediatek,mt6779-mmsys
              - mediatek,mt6795-mmsys
              - mediatek,mt6797-mmsys
              - mediatek,mt8167-mmsys
              - mediatek,mt8173-mmsys
+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties:
              - mediatek,mt2701-pericfg
              - mediatek,mt2712-pericfg
              - mediatek,mt6765-pericfg
              - mediatek,mt6795-pericfg
              - mediatek,mt7622-pericfg
              - mediatek,mt7629-pericfg
              - mediatek,mt8135-pericfg
+1 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ properties:
              - mediatek,mt2712-apmixedsys
              - mediatek,mt6765-apmixedsys
              - mediatek,mt6779-apmixedsys
              - mediatek,mt6795-apmixedsys
              - mediatek,mt7629-apmixedsys
              - mediatek,mt8167-apmixedsys
              - mediatek,mt8183-apmixedsys
+66 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Functional Clock Controller for MT6795

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  - Chun-Jie Chen <chun-jie.chen@mediatek.com>

description: |
  The clock architecture in MediaTek like below
  PLLs -->
          dividers -->
                      muxes
                           -->
                              clock gate

  The devices provide clock gate control in different IP blocks.

properties:
  compatible:
    enum:
      - mediatek,mt6795-mfgcfg
      - mediatek,mt6795-vdecsys
      - mediatek,mt6795-vencsys

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

required:
  - compatible
  - reg
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        mfgcfg: clock-controller@13000000 {
            compatible = "mediatek,mt6795-mfgcfg";
            reg = <0 0x13000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vdecsys: clock-controller@16000000 {
            compatible = "mediatek,mt6795-vdecsys";
            reg = <0 0x16000000 0 0x1000>;
            #clock-cells = <1>;
        };

        vencsys: clock-controller@18000000 {
            compatible = "mediatek,mt6795-vencsys";
            reg = <0 0x18000000 0 0x1000>;
            #clock-cells = <1>;
        };
    };
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