Commit 37eceb69 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.1' of... 

Merge tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driverd updates from Krzysztof Kozlowski:

 - Exynos7885: add FSYS, TREX and MFC clock controllers.
 - Exynos850: add IS and AUD (audio) clock controllers with bindings.
 - ExynosAutov9: add FSYS clock controllers with bindings.
 - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
   controllers, due to duplicated entries.  This is an acceptable ABI
   break: recently developed/added platform so without legacies, acked
   by known users/developers.
 - ExynosAutov9: add few missing Peric 0/1 gates.
 - ExynosAutov9: correct register offsets of few Peric 0/1 clocks.
 - Minor code improvements (use of_device_get_match_data() helper, code
   style).
 - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
   already maintainers that architecture/platform.

* tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
  clk: samsung: exynos850: Implement CMU_MFCMSCL domain
  clk: samsung: exynos850: Implement CMU_IS domain
  clk: samsung: exynos850: Implement CMU_AUD domain
  clk: samsung: exynos850: Style fixes
  clk: samsung: exynosautov9: add fsys1 clock support
  clk: samsung: exynosautov9: add fsys0 clock support
  clk: samsung: exynosautov9: correct register offsets of peric0/c1
  clk: samsung: exynosautov9: add missing gate clks for peric0/c1
  dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
  dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
  dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
  dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
  dt-bindings: clock: exynosautov9: add fsys1 clock definitions
  dt-bindings: clock: exynosautov9: add fys0 clock definitions
  clk: samsung: exynos7885: Add TREX clocks
  clk: samsung: exynos7885: Implement CMU_FSYS domain
  dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
  clk: samsung: exynos-clkout: Use of_device_get_match_data()
parents 568035b0 ef96c458

Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

+69 −0
Original line number Diff line number Diff line
@@ -33,10 +33,13 @@ properties: 
    enum:

      - samsung,exynos850-cmu-top

      - samsung,exynos850-cmu-apm

      - samsung,exynos850-cmu-aud

      - samsung,exynos850-cmu-cmgp

      - samsung,exynos850-cmu-core

      - samsung,exynos850-cmu-dpu

      - samsung,exynos850-cmu-hsi

      - samsung,exynos850-cmu-is

      - samsung,exynos850-cmu-mfcmscl

      - samsung,exynos850-cmu-peri



  clocks:
@@ -88,6 +91,24 @@ allOf: 
            - const: oscclk

            - const: dout_clkcmu_apm_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-aud



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: AUD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_aud



  - if:

      properties:

        compatible:
@@ -172,6 +193,54 @@ allOf: 
            - const: dout_hsi_mmc_card

            - const: dout_hsi_usb20drd



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-is



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_IS bus clock (from CMU_TOP)

            - description: Image Texture Processing core clock (from CMU_TOP)

            - description: Visual Recognition Accelerator clock (from CMU_TOP)

            - description: Geometric Distortion Correction clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_is_bus

            - const: dout_is_itp

            - const: dout_is_vra

            - const: dout_is_gdc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-mfcmscl



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: Multi-Format Codec clock (from CMU_TOP)

            - description: Memory to Memory Scaler clock (from CMU_TOP)

            - description: Multi-Channel Scaler clock (from CMU_TOP)

            - description: JPEG codec clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_mfcmscl_mfc

            - const: dout_mfcmscl_m2m

            - const: dout_mfcmscl_mcsc

            - const: dout_mfcmscl_jpeg



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml

+44 −0
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ properties: 
      - samsung,exynosautov9-cmu-top

      - samsung,exynosautov9-cmu-busmc

      - samsung,exynosautov9-cmu-core

      - samsung,exynosautov9-cmu-fsys0

      - samsung,exynosautov9-cmu-fsys1

      - samsung,exynosautov9-cmu-fsys2

      - samsung,exynosautov9-cmu-peric0

      - samsung,exynosautov9-cmu-peric1
@@ -107,6 +109,48 @@ allOf: 
            - const: oscclk

            - const: dout_clkcmu_core_bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-fsys0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS0 bus clock (from CMU_TOP)

            - description: CMU_FSYS0 pcie clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_fsys0_bus

            - const: dout_clkcmu_fsys0_pcie



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynosautov9-cmu-fsys1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS1 bus clock (from CMU_TOP)

            - description: CMU_FSYS1 mmc card clock (from CMU_TOP)

            - description: CMU_FSYS1 usb clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_clkcmu_fsys1_bus

            - const: dout_clkcmu_fsys1_mmc_card

            - const: dout_clkcmu_fsys1_usbdrd



  - if:

      properties:

        compatible:

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -18022,12 +18022,14 @@ Q: https://patchwork.linuxtv.org/project/linux-media/list/ 
F:	drivers/media/platform/samsung/exynos4-is/









SAMSUNG SOC CLOCK DRIVERS









M:	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>









M:	Sylwester Nawrocki <s.nawrocki@samsung.com>









M:	Tomasz Figa <tomasz.figa@gmail.com>









M:	Chanwoo Choi <cw00.choi@samsung.com>









R:	Alim Akhtar <alim.akhtar@samsung.com>









L:	linux-samsung-soc@vger.kernel.org









S:	Supported









T:	git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git









T:	git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git









F:	Documentation/devicetree/bindings/clock/samsung,*.yaml









F:	Documentation/devicetree/bindings/clock/samsung,s3c*

























drivers/clk/samsung/clk-exynos-clkout.c



+2
−4






























Original line number
Diff line number
Diff line







@@ -81,19 +81,17 @@ MODULE_DEVICE_TABLE(of, exynos_clkout_ids);







static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask)









{









	const struct exynos_clkout_variant *variant;









	const struct of_device_id *match;



















	if (!dev->parent) {









		dev_err(dev, "not instantiated from MFD\n");









		return -EINVAL;









	}



















	match = of_match_device(exynos_clkout_ids, dev->parent);









	if (!match) {









	variant = of_device_get_match_data(dev->parent);









	if (!variant) {









		dev_err(dev, "cannot match parent device\n");









		return -EINVAL;









	}









	variant = match->data;



















	*mux_mask = variant->mux_mask;










































drivers/clk/samsung/clk-exynos7885.c



+200
−7






























Original line number
Diff line number
Diff line







@@ -27,6 +27,11 @@







#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS		0x1014









#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI		0x1018









#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D		0x101c









#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS		0x1028









#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD	0x102c









#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD	0x1030









#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO	0x1034









#define CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD	0x1038









#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS		0x1058









#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0	0x105c









#define CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1	0x1060








@@ -39,6 +44,11 @@







#define CLK_CON_DIV_CLKCMU_CORE_BUS		0x181c









#define CLK_CON_DIV_CLKCMU_CORE_CCI		0x1820









#define CLK_CON_DIV_CLKCMU_CORE_G3D		0x1824









#define CLK_CON_DIV_CLKCMU_FSYS_BUS		0x1844









#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD	0x1848









#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD	0x184c









#define CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO	0x1850









#define CLK_CON_DIV_CLKCMU_FSYS_USB30DRD	0x1854









#define CLK_CON_DIV_CLKCMU_PERI_BUS		0x1874









#define CLK_CON_DIV_CLKCMU_PERI_SPI0		0x1878









#define CLK_CON_DIV_CLKCMU_PERI_SPI1		0x187c








@@ -59,6 +69,11 @@







#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS	0x201c









#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI	0x2020









#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D	0x2024









#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS	0x2044









#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD	0x2048









#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD	0x204c









#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO	0x2050









#define CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD	0x2054









#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS	0x207c









#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0	0x2080









#define CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1	0x2084








@@ -76,6 +91,11 @@ static const unsigned long top_clk_regs[] __initconst = {







	CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,









	CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,









	CLK_CON_MUX_MUX_CLKCMU_CORE_G3D,









	CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS,









	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD,









	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD,









	CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO,









	CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD,









	CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,









	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI0,









	CLK_CON_MUX_MUX_CLKCMU_PERI_SPI1,








@@ -88,6 +108,11 @@ static const unsigned long top_clk_regs[] __initconst = {







	CLK_CON_DIV_CLKCMU_CORE_BUS,









	CLK_CON_DIV_CLKCMU_CORE_CCI,









	CLK_CON_DIV_CLKCMU_CORE_G3D,









	CLK_CON_DIV_CLKCMU_FSYS_BUS,









	CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD,









	CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD,









	CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO,









	CLK_CON_DIV_CLKCMU_FSYS_USB30DRD,









	CLK_CON_DIV_CLKCMU_PERI_BUS,









	CLK_CON_DIV_CLKCMU_PERI_SPI0,









	CLK_CON_DIV_CLKCMU_PERI_SPI1,








@@ -108,6 +133,11 @@ static const unsigned long top_clk_regs[] __initconst = {







	CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,









	CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,









	CLK_CON_GAT_GATE_CLKCMU_CORE_G3D,









	CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS,









	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD,









	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD,









	CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO,









	CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD,









	CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,









	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI0,









	CLK_CON_GAT_GATE_CLKCMU_PERI_SPI1,








@@ -146,6 +176,13 @@ PNAME(mout_peri_usi0_p)		= { "oscclk", "dout_shared0_div4" };







PNAME(mout_peri_usi1_p)		= { "oscclk", "dout_shared0_div4" };









PNAME(mout_peri_usi2_p)		= { "oscclk", "dout_shared0_div4" };



















/* List of parent clocks for Muxes in CMU_TOP: for CMU_FSYS */









PNAME(mout_fsys_bus_p)		= { "dout_shared0_div2", "dout_shared1_div2" };









PNAME(mout_fsys_mmc_card_p)	= { "dout_shared0_div2", "dout_shared1_div2" };









PNAME(mout_fsys_mmc_embd_p)	= { "dout_shared0_div2", "dout_shared1_div2" };









PNAME(mout_fsys_mmc_sdio_p)	= { "dout_shared0_div2", "dout_shared1_div2" };









PNAME(mout_fsys_usb30drd_p)	= { "dout_shared0_div4", "dout_shared1_div4" };



















static const struct samsung_mux_clock top_mux_clks[] __initconst = {









	/* CORE */









	MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,








@@ -174,6 +211,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {







	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI1, 0, 1),









	MUX(CLK_MOUT_PERI_USI2, "mout_peri_usi2", mout_peri_usi2_p,









	    CLK_CON_MUX_MUX_CLKCMU_PERI_USI2, 0, 1),



















	/* FSYS */









	MUX(CLK_MOUT_FSYS_BUS, "mout_fsys_bus", mout_fsys_bus_p,









	    CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1),









	MUX(CLK_MOUT_FSYS_MMC_CARD, "mout_fsys_mmc_card", mout_fsys_mmc_card_p,









	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 1),









	MUX(CLK_MOUT_FSYS_MMC_EMBD, "mout_fsys_mmc_embd", mout_fsys_mmc_embd_p,









	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 1),









	MUX(CLK_MOUT_FSYS_MMC_SDIO, "mout_fsys_mmc_sdio", mout_fsys_mmc_sdio_p,









	    CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_SDIO, 0, 1),









	MUX(CLK_MOUT_FSYS_USB30DRD, "mout_fsys_usb30drd", mout_fsys_usb30drd_p,









	    CLK_CON_MUX_MUX_CLKCMU_FSYS_USB30DRD, 0, 1),









};



















static const struct samsung_div_clock top_div_clks[] __initconst = {








@@ -220,6 +269,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {







	    CLK_CON_DIV_CLKCMU_PERI_USI1, 0, 4),









	DIV(CLK_DOUT_PERI_USI2, "dout_peri_usi2", "gout_peri_usi2",









	    CLK_CON_DIV_CLKCMU_PERI_USI2, 0, 4),



















	/* FSYS */









	DIV(CLK_DOUT_FSYS_BUS, "dout_fsys_bus", "gout_fsys_bus",









	    CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4),









	DIV(CLK_DOUT_FSYS_MMC_CARD, "dout_fsys_mmc_card", "gout_fsys_mmc_card",









	    CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9),









	DIV(CLK_DOUT_FSYS_MMC_EMBD, "dout_fsys_mmc_embd", "gout_fsys_mmc_embd",









	    CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9),









	DIV(CLK_DOUT_FSYS_MMC_SDIO, "dout_fsys_mmc_sdio", "gout_fsys_mmc_sdio",









	    CLK_CON_DIV_CLKCMU_FSYS_MMC_SDIO, 0, 9),









	DIV(CLK_DOUT_FSYS_USB30DRD, "dout_fsys_usb30drd", "gout_fsys_usb30drd",









	    CLK_CON_DIV_CLKCMU_FSYS_USB30DRD, 0, 4),









};



















static const struct samsung_gate_clock top_gate_clks[] __initconst = {








@@ -250,6 +311,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {







	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI1, 21, 0, 0),









	GATE(CLK_GOUT_PERI_USI2, "gout_peri_usi2", "mout_peri_usi2",









	     CLK_CON_GAT_GATE_CLKCMU_PERI_USI2, 21, 0, 0),



















	/* FSYS */









	GATE(CLK_GOUT_FSYS_BUS, "gout_fsys_bus", "mout_fsys_bus",









	     CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0),









	GATE(CLK_GOUT_FSYS_MMC_CARD, "gout_fsys_mmc_card", "mout_fsys_mmc_card",









	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0),









	GATE(CLK_GOUT_FSYS_MMC_EMBD, "gout_fsys_mmc_embd", "mout_fsys_mmc_embd",









	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0),









	GATE(CLK_GOUT_FSYS_MMC_SDIO, "gout_fsys_mmc_sdio", "mout_fsys_mmc_sdio",









	     CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_SDIO, 21, 0, 0),









	GATE(CLK_GOUT_FSYS_USB30DRD, "gout_fsys_usb30drd", "mout_fsys_usb30drd",









	     CLK_CON_GAT_GATE_CLKCMU_FSYS_USB30DRD, 21, 0, 0),









};



















static const struct samsung_cmu_info top_cmu_info __initconst = {








@@ -505,6 +578,13 @@ CLK_OF_DECLARE(exynos7885_cmu_peri, "samsung,exynos7885-cmu-peri",







#define CLK_CON_DIV_DIV_CLK_CORE_BUSP			0x1800









#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK		0x2054









#define CLK_CON_GAT_GOUT_CORE_GIC400_CLK		0x2058









#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK		0x215c









#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK		0x2160









#define CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK		0x2164









#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE	0x2168









#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE	0x216c









#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK		0x2170









#define CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE	0x2174



















static const unsigned long core_clk_regs[] __initconst = {









	PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,








@@ -514,6 +594,13 @@ static const unsigned long core_clk_regs[] __initconst = {







	CLK_CON_DIV_DIV_CLK_CORE_BUSP,









	CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,









	CLK_CON_GAT_GOUT_CORE_GIC400_CLK,









	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK,









	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK,









	CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK,









	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE,









	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE,









	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK,









	CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE,









};



















/* List of parent clocks for Muxes in CMU_CORE */








@@ -545,6 +632,27 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = {







	/* GIC (interrupt controller) clock must be always running */









	GATE(CLK_GOUT_GIC400_CLK, "gout_gic400_clk", "mout_core_gic",









	     CLK_CON_GAT_GOUT_CORE_GIC400_CLK, 21, CLK_IS_CRITICAL, 0),









	/*









	 * TREX D and P Core (seems to be related to "bus traffic shaper")









	 * clocks must always be running









	 */









	GATE(CLK_GOUT_TREX_D_CORE_ACLK, "gout_trex_d_core_aclk", "mout_core_bus_user",









	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_ACLK, 21, CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_D_CORE_GCLK, "gout_trex_d_core_gclk", "mout_core_g3d_user",









	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_GCLK, 21, CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_D_CORE_PCLK, "gout_trex_d_core_pclk", "dout_core_busp",









	     CLK_CON_GAT_GOUT_CORE_TREX_D_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_P_CORE_ACLK_P_CORE, "gout_trex_p_core_aclk_p_core",









	     "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_ACLK_P_CORE, 21,









	     CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_P_CORE_CCLK_P_CORE, "gout_trex_p_core_cclk_p_core",









	     "mout_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_CCLK_P_CORE, 21,









	     CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_P_CORE_PCLK, "gout_trex_p_core_pclk", "dout_core_busp",









	     CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK, 21, CLK_IS_CRITICAL, 0),









	GATE(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE, "gout_trex_p_core_pclk_p_core",









	     "dout_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_CORE_PCLK_P_CORE, 21,









	     CLK_IS_CRITICAL, 0),









};



















static const struct samsung_cmu_info core_cmu_info __initconst = {








@@ -560,6 +668,88 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {







	.clk_name		= "dout_core_bus",









};



















/* ---- CMU_FSYS ------------------------------------------------------------ */



















/* Register Offset definitions for CMU_FSYS (0x13400000) */









#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER	0x0100









#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER	0x0120









#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER	0x0140









#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER	0x0160









#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER	0x0180









#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK	0x2030









#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN	0x2034









#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK	0x2038









#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN	0x203c









#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK	0x2040









#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN	0x2044



















static const unsigned long fsys_clk_regs[] __initconst = {









	PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,









	PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,









	PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,









	PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,









	PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,









	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,









	CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,









	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,









	CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,









	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,









	CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,









};



















/* List of parent clocks for Muxes in CMU_FSYS */









PNAME(mout_fsys_bus_user_p)		= { "oscclk", "dout_fsys_bus" };









PNAME(mout_fsys_mmc_card_user_p)	= { "oscclk", "dout_fsys_mmc_card" };









PNAME(mout_fsys_mmc_embd_user_p)	= { "oscclk", "dout_fsys_mmc_embd" };









PNAME(mout_fsys_mmc_sdio_user_p)	= { "oscclk", "dout_fsys_mmc_sdio" };









PNAME(mout_fsys_usb30drd_user_p)	= { "oscclk", "dout_fsys_usb30drd" };



















static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {









	MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,









	    PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1),









	MUX_F(CLK_MOUT_FSYS_MMC_CARD_USER, "mout_fsys_mmc_card_user",









	      mout_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,









	      4, 1, CLK_SET_RATE_PARENT, 0),









	MUX_F(CLK_MOUT_FSYS_MMC_EMBD_USER, "mout_fsys_mmc_embd_user",









	      mout_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,









	      4, 1, CLK_SET_RATE_PARENT, 0),









	MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",









	      mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,









	      4, 1, CLK_SET_RATE_PARENT, 0),









	MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",









	      mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,









	      4, 1, CLK_SET_RATE_PARENT, 0),









};



















static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {









	GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",









	     CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),









	GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",









	     "mout_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,









	     21, CLK_SET_RATE_PARENT, 0),









	GATE(CLK_GOUT_MMC_EMBD_ACLK, "gout_mmc_embd_aclk", "mout_fsys_bus_user",









	     CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK, 21, 0, 0),









	GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",









	     "mout_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,









	     21, CLK_SET_RATE_PARENT, 0),









	GATE(CLK_GOUT_MMC_SDIO_ACLK, "gout_mmc_sdio_aclk", "mout_fsys_bus_user",









	     CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK, 21, 0, 0),









	GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",









	     "mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,









	     21, CLK_SET_RATE_PARENT, 0),









};



















static const struct samsung_cmu_info fsys_cmu_info __initconst = {









	.mux_clks		= fsys_mux_clks,









	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),









	.gate_clks		= fsys_gate_clks,









	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),









	.nr_clk_ids		= FSYS_NR_CLK,









	.clk_regs		= fsys_clk_regs,









	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),









	.clk_name		= "dout_fsys_bus",









};



















/* ---- platform_driver ----------------------------------------------------- */



















static int __init exynos7885_cmu_probe(struct platform_device *pdev)








@@ -577,6 +767,9 @@ static const struct of_device_id exynos7885_cmu_of_match[] = {







	{









		.compatible = "samsung,exynos7885-cmu-core",









		.data = &core_cmu_info,









	}, {









		.compatible = "samsung,exynos7885-cmu-fsys",









		.data = &fsys_cmu_info,









	}, {









	},









};