Commit 49f4c2d1 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and...

Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next

 - Miscellaneous of_node_put() fixes
 - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
 - Convert gpio-clk-gate binding to YAML
 - Various fixes to AMD/Xilinx Zynqmp clk driver
 - Graduate AMD/Xilinx "clocking wizard" driver from staging

* clk-ofnode:
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: tegra20: Fix refcount leak in tegra20_clock_init
  clk: tegra: Fix refcount leak in tegra114_clock_init
  clk: tegra: Fix refcount leak in tegra210_clock_init
  clk: sprd: Hold reference returned by of_get_parent()
  clk: berlin: Add of_node_put() for of_get_parent()
  clk: at91: dt-compat: Hold reference returned by of_get_parent()
  clk: qoriq: Hold reference returned by of_get_parent()
  clk: oxnas: Hold reference returned by of_get_parent()
  clk: st: Hold reference returned by of_get_parent()
  clk: tegra: Add missing of_node_put()
  clk: meson: Hold reference returned by of_get_parent()
  clk: nomadik: Add missing of_node_put()

* clk-bindings:
  dt-bindings: clock: drop minItems equal to maxItems
  dt-bindings: clock: gpio-gate-clock: Convert to json-schema
  dt-bindings: clock: Move versaclock.h to dt-bindings/clock
  dt-bindings: clock: Move lochnagar.h to dt-bindings/clock

* clk-cleanup:
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: nxp: fix typo in comment
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clkdev: Simplify devm_clk_hw_register_clkdev() function
  clkdev: Remove never used devm_clk_release_clkdev()
  clk: Remove never used devm_of_clk_del_provider()
  clk: pistachio: Fix initconst confusion
  clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data
  clk: do not initialize ret
  clk: remove extra empty line
  clk: Fix comment typo
  clk: move from strlcpy with unused retval to strscpy

* clk-zynq:
  clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate
  clk: zynqmp: Check the return type zynqmp_pm_query_data
  clk: zynqmp: Add a check for NULL pointer
  clk: zynqmp: Replaced strncpy() with strscpy()
  clk: zynqmp: Fix stack-out-of-bounds in strncpy`
  clk: zynqmp: make bestdiv unsigned

* clk-xilinx:
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: clocking-wizard: Update the compatible
  clk: clocking-wizard: Fix the reconfig for 5.2
  clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs
  clk: clocking-wizard: Move clocking-wizard out
  dt-bindings: add documentation of xilinx clocking wizard
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+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ properties:
  clocks:
    description:
      Common clock binding for CLK_IN, XTI/REF_CLK
    minItems: 2
    maxItems: 2

  clock-names:
+0 −21
Original line number Diff line number Diff line
Binding for simple gpio gated clock.

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be "gpio-gate-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- enable-gpios : GPIO reference for enabling and disabling the clock.

Optional properties:
- clocks: Maximum of one parent clock is supported.

Example:
	clock {
		compatible = "gpio-gate-clock";
		clocks = <&parentclk>;
		#clock-cells = <0>;
		enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
	};
+42 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/gpio-gate-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Simple GPIO clock gate

maintainers:
  - Jyri Sarha <jsarha@ti.com>

properties:
  compatible:
    const: gpio-gate-clock

  clocks:
    maxItems: 1

  '#clock-cells':
    const: 0

  enable-gpios:
    description: GPIO reference for enabling and disabling the clock.
    maxItems: 1

required:
  - compatible
  - '#clock-cells'
  - enable-gpios

additionalProperties: false

examples:
  - |
    #include <dt-bindings/gpio/gpio.h>

    clock {
        compatible = "gpio-gate-clock";
        clocks = <&parentclk>;
        #clock-cells = <0>;
        enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
    };
+2 −2
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ patternProperties:
    properties:
      idt,mode:
        description:
          The output drive mode. Values defined in dt-bindings/clk/versaclock.h
          The output drive mode. Values defined in dt-bindings/clock/versaclock.h
        $ref: /schemas/types.yaml#/definitions/uint32
        minimum: 0
        maximum: 6
@@ -151,7 +151,7 @@ additionalProperties: false

examples:
  - |
    #include <dt-bindings/clk/versaclock.h>
    #include <dt-bindings/clock/versaclock.h>

    /* 25MHz reference crystal */
    ref25: ref25m {
+0 −2
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ properties:
    maxItems: 1

  clocks:
    minItems: 4
    maxItems: 4

  clock-names:
@@ -64,7 +63,6 @@ properties:
    maxItems: 1

  resets:
    minItems: 2
    maxItems: 2

  reset-names:
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