Commit 12198d91 authored by Lukas Bulwahn's avatar Lukas Bulwahn Committed by Stephen Boyd
Browse files

clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x 



Commit 7dd33764 ("ARM: davinci: Delete DM644x board files") and commit
b4aed01d ("ARM: davinci: Delete DM646x board files") removes the
support for DaVinci DM644x and DM646x boards.

Hence, remove the PLL and PSC clock descriptions for those boards as well.

Signed-off-by: default avatarLukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20220720082934.17741-1-lukas.bulwahn@gmail.com


Reviewed-by: default avatarDavid Lechner <david@lechnology.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 568035b0

drivers/clk/davinci/Makefile

+0 −4
Original line number Diff line number Diff line
@@ -8,14 +8,10 @@ obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o 
obj-$(CONFIG_ARCH_DAVINCI_DA850)	+= pll-da850.o

obj-$(CONFIG_ARCH_DAVINCI_DM355)	+= pll-dm355.o

obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= pll-dm365.o

obj-$(CONFIG_ARCH_DAVINCI_DM644x)	+= pll-dm644x.o

obj-$(CONFIG_ARCH_DAVINCI_DM646x)	+= pll-dm646x.o



obj-y += psc.o

obj-$(CONFIG_ARCH_DAVINCI_DA830)	+= psc-da830.o

obj-$(CONFIG_ARCH_DAVINCI_DA850)	+= psc-da850.o

obj-$(CONFIG_ARCH_DAVINCI_DM355)	+= psc-dm355.o

obj-$(CONFIG_ARCH_DAVINCI_DM365)	+= psc-dm365.o

obj-$(CONFIG_ARCH_DAVINCI_DM644x)	+= psc-dm644x.o

obj-$(CONFIG_ARCH_DAVINCI_DM646x)	+= psc-dm646x.o

endif

drivers/clk/davinci/pll-dm644x.c

deleted100644 → 0
+0 −81
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * PLL clock descriptions for TI DM644X

 *

 * Copyright (C) 2018 David Lechner <david@lechnology.com>

 */



#include <linux/bitops.h>

#include <linux/clk/davinci.h>

#include <linux/clkdev.h>

#include <linux/init.h>

#include <linux/types.h>



#include "pll.h"



static const struct davinci_pll_clk_info dm644x_pll1_info = {

	.name = "pll1",

	.pllm_mask = GENMASK(4, 0),

	.pllm_min = 1,

	.pllm_max = 32,

	.pllout_min_rate = 400000000,

	.pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */

	.flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,

};



SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);



int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);

	clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);

	clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);

	clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);

	clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");



	clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);

	clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");



	davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);



	return 0;

}



static const struct davinci_pll_clk_info dm644x_pll2_info = {

	.name = "pll2",

	.pllm_mask = GENMASK(4, 0),

	.pllm_min = 1,

	.pllm_max = 32,

	.pllout_min_rate = 400000000,

	.pllout_max_rate = 900000000,

	.flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,

};



SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);

SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);



int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);



	davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);



	davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);



	return 0;

}

drivers/clk/davinci/pll-dm646x.c

deleted100644 → 0
+0 −85
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * PLL clock descriptions for TI DM646X

 *

 * Copyright (C) 2018 David Lechner <david@lechnology.com>

 */



#include <linux/clk-provider.h>

#include <linux/clk/davinci.h>

#include <linux/clkdev.h>

#include <linux/init.h>

#include <linux/types.h>



#include "pll.h"



static const struct davinci_pll_clk_info dm646x_pll1_info = {

	.name = "pll1",

	.pllm_mask = GENMASK(4, 0),

	.pllm_min = 14,

	.pllm_max = 32,

	.flags = PLL_HAS_CLKMODE,

};



SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);

SYSCLK(4, pll1_sysclk4, pll1_pllen, 4, 0);

SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, 0);

SYSCLK(6, pll1_sysclk6, pll1_pllen, 4, 0);

SYSCLK(8, pll1_sysclk8, pll1_pllen, 4, 0);

SYSCLK(9, pll1_sysclk9, pll1_pllen, 4, 0);



int dm646x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	struct clk *clk;



	davinci_pll_clk_register(dev, &dm646x_pll1_info, "ref_clk", base, cfgchip);



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);

	clk_register_clkdev(clk, "pll1_sysclk1", "dm646x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);

	clk_register_clkdev(clk, "pll1_sysclk2", "dm646x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);

	clk_register_clkdev(clk, "pll1_sysclk3", "dm646x-psc");

	clk_register_clkdev(clk, NULL, "davinci-wdt");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);

	clk_register_clkdev(clk, "pll1_sysclk4", "dm646x-psc");



	clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);

	clk_register_clkdev(clk, "pll1_sysclk5", "dm646x-psc");



	davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);



	davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);



	davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);



	davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);



	davinci_pll_auxclk_register(dev, "pll1_auxclk", base);



	return 0;

}



static const struct davinci_pll_clk_info dm646x_pll2_info = {

	.name = "pll2",

	.pllm_mask = GENMASK(4, 0),

	.pllm_min = 14,

	.pllm_max = 32,

	.flags = 0,

};



SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);



int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)

{

	davinci_pll_clk_register(dev, &dm646x_pll2_info, "oscin", base, cfgchip);



	davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);



	return 0;

}

drivers/clk/davinci/pll.c

+0 −8
Original line number Diff line number Diff line
@@ -889,14 +889,6 @@ static const struct platform_device_id davinci_pll_id_table[] = { 
#ifdef CONFIG_ARCH_DAVINCI_DM365

	{ .name = "dm365-pll1",  .driver_data = (kernel_ulong_t)dm365_pll1_init  },

	{ .name = "dm365-pll2",  .driver_data = (kernel_ulong_t)dm365_pll2_init  },

#endif

#ifdef CONFIG_ARCH_DAVINCI_DM644x

	{ .name = "dm644x-pll1", .driver_data = (kernel_ulong_t)dm644x_pll1_init },

	{ .name = "dm644x-pll2", .driver_data = (kernel_ulong_t)dm644x_pll2_init },

#endif

#ifdef CONFIG_ARCH_DAVINCI_DM646x

	{ .name = "dm646x-pll1", .driver_data = (kernel_ulong_t)dm646x_pll1_init },

	{ .name = "dm646x-pll2", .driver_data = (kernel_ulong_t)dm646x_pll2_init },

#endif

	{ }

};

drivers/clk/davinci/pll.h

+0 −6
Original line number Diff line number Diff line
@@ -130,11 +130,5 @@ int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cf 
#ifdef CONFIG_ARCH_DAVINCI_DM355

int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);

#endif

#ifdef CONFIG_ARCH_DAVINCI_DM644x

int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);

#endif

#ifdef CONFIG_ARCH_DAVINCI_DM646x

int dm646x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip);

#endif



#endif /* __CLK_DAVINCI_PLL_H___ */