Commit d46adccb authored by Fabien Parent's avatar Fabien Parent Committed by Stephen Boyd
Browse files

clk: mediatek: add driver for MT8365 SoC

parent 083cc5e4
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@@ -645,6 +645,56 @@ config COMMON_CLK_MT8195
        help
          This driver supports MediaTek MT8195 clocks.

config COMMON_CLK_MT8365
	tristate "Clock driver for MediaTek MT8365"
	depends on ARCH_MEDIATEK || COMPILE_TEST
	select COMMON_CLK_MEDIATEK
	default ARCH_MEDIATEK && ARM64
	help
	  This driver supports MediaTek MT8365 basic clocks.

config COMMON_CLK_MT8365_APU
	tristate "Clock driver for MediaTek MT8365 apu"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 apu clocks.

config COMMON_CLK_MT8365_CAM
	tristate "Clock driver for MediaTek MT8365 cam"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 cam clocks.

config COMMON_CLK_MT8365_MFG
	tristate "Clock driver for MediaTek MT8365 mfg"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 mfg clocks.

config COMMON_CLK_MT8365_MMSYS
	tristate "Clock driver for MediaTek MT8365 mmsys"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 mmsys clocks.

config COMMON_CLK_MT8365_VDEC
	tristate "Clock driver for MediaTek MT8365 vdec"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 vdec clocks.

config COMMON_CLK_MT8365_VENC
	tristate "Clock driver for MediaTek MT8365 venc"
	depends on COMMON_CLK_MT8365
	default COMMON_CLK_MT8365
	help
	  This driver supports MediaTek MT8365 venc clocks.

config COMMON_CLK_MT8516
	bool "Clock driver for MediaTek MT8516"
	depends on ARCH_MEDIATEK || COMPILE_TEST
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@@ -103,5 +103,12 @@ obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o
				   clk-mt8195-venc.o clk-mt8195-vpp0.o clk-mt8195-vpp1.o \
				   clk-mt8195-wpe.o clk-mt8195-imp_iic_wrap.o \
				   clk-mt8195-apusys_pll.o
obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365.o
obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
obj-$(CONFIG_COMMON_CLK_MT8365_MFG) += clk-mt8365-mfg.o
obj-$(CONFIG_COMMON_CLK_MT8365_MMSYS) += clk-mt8365-mm.o
obj-$(CONFIG_COMMON_CLK_MT8365_VDEC) += clk-mt8365-vdec.o
obj-$(CONFIG_COMMON_CLK_MT8365_VENC) += clk-mt8365-venc.o
obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
+55 −0
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 MediaTek Inc.
 */

#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"

static const struct mtk_gate_regs apu_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

#define GATE_APU(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \
			 &mtk_clk_gate_ops_setclr)

static const struct mtk_gate apu_clks[] = {
	GATE_APU(CLK_APU_AHB, "apu_ahb", "ifr_apu_axi", 5),
	GATE_APU(CLK_APU_EDMA, "apu_edma", "apu_sel", 4),
	GATE_APU(CLK_APU_IF_CK, "apu_if_ck", "apu_if_sel", 3),
	GATE_APU(CLK_APU_JTAG, "apu_jtag", "clk26m", 2),
	GATE_APU(CLK_APU_AXI, "apu_axi", "apu_sel", 1),
	GATE_APU(CLK_APU_IPU_CK, "apu_ck", "apu_sel", 0),
};

static const struct mtk_clk_desc apu_desc = {
	.clks = apu_clks,
	.num_clks = ARRAY_SIZE(apu_clks),
};

static const struct of_device_id of_match_clk_mt8365_apu[] = {
	{
		.compatible = "mediatek,mt8365-apu",
		.data = &apu_desc,
	}, {
		/* sentinel */
	}
};

static struct platform_driver clk_mt8365_apu_drv = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,
	.driver = {
		.name = "clk-mt8365-apu",
		.of_match_table = of_match_clk_mt8365_apu,
	},
};
builtin_platform_driver(clk_mt8365_apu_drv);
MODULE_LICENSE("GPL");
+57 −0
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 MediaTek Inc.
 */

#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"

static const struct mtk_gate_regs cam_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

#define GATE_CAM(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
			 &mtk_clk_gate_ops_setclr)

static const struct mtk_gate cam_clks[] = {
	GATE_CAM(CLK_CAM_LARB2, "cam_larb2", "mm_sel", 0),
	GATE_CAM(CLK_CAM, "cam", "mm_sel", 6),
	GATE_CAM(CLK_CAMTG, "camtg", "mm_sel", 7),
	GATE_CAM(CLK_CAM_SENIF, "cam_senif", "mm_sel", 8),
	GATE_CAM(CLK_CAMSV0, "camsv0", "mm_sel", 9),
	GATE_CAM(CLK_CAMSV1, "camsv1", "mm_sel", 10),
	GATE_CAM(CLK_CAM_FDVT, "cam_fdvt", "mm_sel", 11),
	GATE_CAM(CLK_CAM_WPE, "cam_wpe", "mm_sel", 12),
};

static const struct mtk_clk_desc cam_desc = {
	.clks = cam_clks,
	.num_clks = ARRAY_SIZE(cam_clks),
};

static const struct of_device_id of_match_clk_mt8365_cam[] = {
	{
		.compatible = "mediatek,mt8365-imgsys",
		.data = &cam_desc,
	}, {
		/* sentinel */
	}
};

static struct platform_driver clk_mt8365_cam_drv = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,
	.driver = {
		.name = "clk-mt8365-cam",
		.of_match_table = of_match_clk_mt8365_cam,
	},
};
builtin_platform_driver(clk_mt8365_cam_drv);
MODULE_LICENSE("GPL");
+63 −0
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// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2022 MediaTek Inc.
 */

#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <linux/clk-provider.h>
#include <linux/platform_device.h>

#include "clk-gate.h"
#include "clk-mtk.h"

static const struct mtk_gate_regs mfg0_cg_regs = {
	.set_ofs = 0x4,
	.clr_ofs = 0x8,
	.sta_ofs = 0x0,
};

static const struct mtk_gate_regs mfg1_cg_regs = {
	.set_ofs = 0x280,
	.clr_ofs = 0x280,
	.sta_ofs = 0x280,
};

#define GATE_MFG0(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \
			 &mtk_clk_gate_ops_setclr)

#define GATE_MFG1(_id, _name, _parent, _shift) \
		GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \
			 &mtk_clk_gate_ops_no_setclr)

static const struct mtk_gate mfg_clks[] = {
	/* MFG0 */
	GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
	/* MFG1 */
	GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24),
};

static const struct mtk_clk_desc mfg_desc = {
	.clks = mfg_clks,
	.num_clks = ARRAY_SIZE(mfg_clks),
};

static const struct of_device_id of_match_clk_mt8365_mfg[] = {
	{
		.compatible = "mediatek,mt8365-mfgcfg",
		.data = &mfg_desc,
	}, {
		/* sentinel */
	}
};

static struct platform_driver clk_mt8365_mfg_drv = {
	.probe = mtk_clk_simple_probe,
	.remove = mtk_clk_simple_remove,
	.driver = {
		.name = "clk-mt8365-mfg",
		.of_match_table = of_match_clk_mt8365_mfg,
	},
};
builtin_platform_driver(clk_mt8365_mfg_drv);
MODULE_LICENSE("GPL");
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