- Nov 03, 2015
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Samuel Pitoiset authored
Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Martin Peres authored
I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Martin Peres authored
Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by:
Martin Peres <martin.peres@free.fr>
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Martin Peres authored
Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by:
Martin Peres <martin.peres@free.fr>
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Martin Peres authored
This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Martin Peres authored
Signed-off-by:
Martin Peres <martin.peres@free.fr> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
The pci_dma_* functions are now superseeded in the kernel by the DMA API. Make the conversion to this more generic API. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Use the IOMMU bit specified in platform data instead of hardcoding it to the bit used by current Tegra GPUs. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
The Great Nouveau Refactoring Take II brought us a lot of goodness, including acquire/release methods that are called before and after an instobj is modified. These functions can be used as synchronization points to manage CPU/GPU coherency if we modify an instobj using the CPU. This patch replaces the legacy and slow PRAMIN access for gk20a instmem with CPU mappings and writes. A LRU list is used to unmap unused mappings after a certain threshold (currently 1MB) of mapped instobjs is reached. This allows mappings to be reused most of the time. Accessing instobjs using the CPU requires to maintain the GPU L2 cache, which we do in the acquire/release functions. This triggers a lot of L2 flushes/invalidates, but most of them are performed on an empty cache (and thus return immediately), and overall context setup performance greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a simple libdrm program). Making L2 management more explicit should allow us to grab some more performance in the future. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
No longer required in a lot of cases, as objects are identified over NVIF via an alternate mechanism since the rework. Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Ilia Mirkin authored
On nv50+, we restrict the valid domains to just the one where the buffer was originally created. However after the buffer is evicted to system memory, we might move it back to a different domain that was not originally valid. When sharing the buffer and retrieving its GEM_INFO data, we still want the domain that will be valid for this buffer in a pushbuf, not the one where it currently happens to be. This resolves fdo#92504 and several others. These are due to suspend evicting all buffers, making it more likely that they temporarily end up in the wrong place. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92504 Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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- Oct 30, 2015
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
Few more drm-misc stragglers for 4.4. Big thing is the generic probe for imx/rockchip/armada (but the variant for msm/rpi/exynos is still missing). Also the hdmi clocking fixes from Ville which was a lot of confusion about which tree it should be applied to ;-) * tag 'topic/drm-misc-2015-10-22' of git://anongit.freedesktop.org/drm-intel: drm: correctly check failed allocation vga_switcheroo: Constify vga_switcheroo_handler drm/armada: Convert the probe function to the generic drm_of_component_probe() drm/rockchip: Convert the probe function to the generic drm_of_component_probe() drm/imx: Convert the probe function to the generic drm_of_component_probe() drm: Introduce generic probe function for component based masters. drm/edid: Round to closest when computing the CEA/HDMI alternate clock drm/edid: Fix up clock for CEA/HDMI modes specified via detailed timings
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
More amdgpu and radeon stuff for drm-next. Stoney support is the big change. The rest is just bug fixes and code cleanups. The Stoney stuff is pretty low impact with respect to existing chips. * 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: change VM size default to 64GB drm/amdgpu: add Stoney pci ids drm/amdgpu: update the core VI support for Stoney drm/amdgpu: add VCE support for Stoney (v2) drm/amdgpu: add UVD support for Stoney drm/amdgpu: add GFX support for Stoney (v2) drm/amdgpu: add SDMA support for Stoney (v2) drm/amdgpu: add DCE support for Stoney drm/amdgpu: Update SMC/DPM for Stoney drm/amdgpu: add GMC support for Stoney drm/amdgpu: add Stoney chip family drm/amdgpu: fix the broken vm->mutex V2 drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any() drm/amdgpu: remove the exclusive lock drm/amdgpu: remove old lockup detection infrastructure drm: fix trivial typos drm/amdgpu/dce: simplify suspend/resume drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet drm/radeon: Use rdev->gem.mutex to protect hyperz/cmask owners
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2015-10-22' of git://anongit.freedesktop.org/drm-intel into drm-next Bunch of -fixes for 4.4. Well not just, I've left the mmio/register work from Ville in here since it's low-risk but lots of churn all over. * tag 'drm-intel-next-fixes-2015-10-22' of git://anongit.freedesktop.org/drm-intel: (23 commits) drm/i915: Use round to closest when computing the CEA 1.001 pixel clocks drm/i915: Kill the leftover RMW from ivb_sprite_disable() drm/i915: restore ggtt double-bind avoidance drm/i915/skl: Enable pipe gamma for sprite planes. drm/i915/skl+: Enable pipe CSC on cursor planes. (v2) MAINTAINERS: add link to the Intel Graphics for Linux web site drm/i915: Move skl/bxt gt specific workarounds to ring init drm/i915: Drop i915_gem_obj_is_pinned() from set-cache-level drm/i915: revert a few more watermark commits drm/i915: Remove dev_priv argument from NEEDS_FORCE_WAKE drm/i915: Clean up LVDS register handling drm/i915: Throw out some useless variables drm/i915: Parametrize and fix SWF registers drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc. drm/i915: Turn GEN5_ASSERT_IIR_IS_ZERO() into a function drm/i915: Fix a few bad hex numbers in register defines drm/i915: Protect register macro arguments drm/i915: Include gpio_mmio_base in GMBUS reg defines drm/i915: Parametrize HSW video DIP data registers drm/i915: Eliminate weird parameter inversion from BXT PPS registers ...
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- Oct 23, 2015
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git://people.freedesktop.org/~robclark/linuxDave Airlie authored
A bit smaller pull this time. Few minor things, plus initial support for msm8996 (snapdragon 820).. Sorry, a bit latish, was hoping to get some 8960/8064 DSI stuff included. But still waiting on the v2 of the patchset (just pending some minor review comments). It would be nice to get the DSI patches merged since it would help some folks trying to get upstream kernel running on n4/n7 and xperia z and wanting to write some more panel drivers. Also, waiting for OCMEM driver to get merged via other trees and then I have a small bit to go along with that to make the gpu actually work on devices w/ OCMEM (snapdragon 800, 805, etc). So maybe a second later pull req, time permitting. * 'msm-next' of git://people.freedesktop.org/~robclark/linux: drm/msm: Remove local fbdev emulation Kconfig option drm/msm/mdp5: Basic support for MDP5 v1.7 (MSM8996) drm/msm/mdp: Add Software Pixel Extension support drm/msm/mdp5: Use the newly introduced enum mdp_component_type drm/msm/hdmi: Add basic HDMI support for msm8996 drm/msm/mdp5: Avoid printing error messages for optional clocks drm/msm: Fix IOMMU clean up path in case msm_iommu_new() fails drm/msm/mdp5: remove the cfg pointer from SMP struct drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY drm: msm: dsi: Don't attempt changing voltage of switches drm/msm: update generated headers
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Archit Taneja authored
DRM_MSM_FBDEV config is used to enable/disable fbdev emulation for the msm kms driver. Replace this with the top level DRM_FBDEV_EMULATION config option where applicable. This also prevents build breaks caused by undefined drm_fb_helper_* functions when legacy fbdev support was disabled. Signed-off-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
This change adds the basic MDP5 support for MSM8996. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
In order to produce an image, the scalar needs to be fed extra pixels. These top/bottom/left/right values depend on a various of factors, including resolution, scaling type, phase step and initial phase. Pixel Extension are programmed by hardware in most targets - and can be overwritten by software. For some targets (e.g.: msm8996), software *must* program those registers. In order to ease this computation, let's always use bilinear filters, which are easier to program from kernel. Eventually, all of these values will come down from user space for better quality. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
When calculating phase steps, let's use the same enum mdp_component_type in order to ease the readability; 0/1 indexes are a bit confusing and we now have explicit values to index this type of arrays. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
The HDMI controller is new in MDP5 v1.7. As of now, this change doesn't reflect the novelty and only adds the basics so the probe gets triggered. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
The current behavior is to try to get optional clocks and print a dev_err message in case of failure. This looks rather confusing and may increase with the amount of optional clocks. We may need a cleaner way to handle per-device clocks but in the meantime, let's reduce the amount of dev_err messages during the probe. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
msm_iommu_new() can fail and this change makes sure that we detect the failure and free the allocated domain before going any further. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Stephane Viau authored
We want to make sure we control all the information being passed down to SMP block. Having access to the cfg pointer here may create bad things in the future. Signed-off-by:
Stephane Viau <sviau@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Hai Li authored
The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by:
Hai Li <hali@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Bjorn Andersson authored
In some configurations the supplies are voltage switches and not LDOs, making the set voltage call to fail. Check with the regulator framework if the supply can change voltage before attempting. Signed-off-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by:
Archit Taneja <architt@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
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Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@gmail.com>
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- Oct 22, 2015
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git://linuxtv.org/pinchartl/fbdevDave Airlie authored
rcar-du support for r8a7793/4 * 'drm/next/du' of git://linuxtv.org/pinchartl/fbdev: drm: rcar-du: Add support for the R8A7794 DU drm: rcar-du: Add support for the R8A7793 DU
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http://github.com/anholt/linuxDave Airlie authored
This pull request introduces the vc4 driver, for kernel modesetting on the Raspberry Pi (bcm2835/bcm2836 architectures). It currently supports a display plane and cursor on the HDMI output. The driver doesn't do 3D, power management, or overlay planes yet. [airlied: fixup the enable/disable vblank APIs] Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> * tag 'drm-vc4-next-2015-10-21' of http://github.com/anholt/linux: drm/vc4: Allow vblank to be disabled drm/vc4: Use the fbdev_cma helpers drm/vc4: Add KMS support for Raspberry Pi. drm/vc4: Add devicetree bindings for VC4.
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Christian König authored
That's still small enough to not waste to much memory on PD/PTs. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Li authored
Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Li authored
Add core VI enablement for Stoney. Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Li authored
Stoney is VCE 3.x single. v2: Stoney is single pipe like Fiji Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Li authored
Stoney is UVD 6.x. Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Samuel Li authored
Stoney is GFX 8.1. v2: update to latest golden settings Signed-off-by:
Samuel Li <samuel.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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