drm/msm/dsi: Updata LNn_CFG4 register settings for 28nm PHY
The current settings for 28nm PHY data lane CFG4 registers do not work with certain panels. This change is to modify them to hw recommended values. Signed-off-by:Hai Li <hali@codeaurora.org> Signed-off-by:
Rob Clark <robdclark@gmail.com>
parent
556a76e5
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