- Oct 21, 2011
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Adam Jackson authored
This is general TMDS detect, not HDMI specifically. Signed-off-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Adam Jackson authored
I can't think of any sensible reason to limit this to a mask of 0x0f, ie, SDVO_OUTPUT_{TMDS,RGB,CVBS,SVID}0. Signed-off-by:
Adam Jackson <ajax@redhat.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Adam Jackson authored
I have no evidence for this byte being used this way, and lots of counterexamples. Restore the struct to its empirical definition and patch up gmbus setup to match. Signed-off-by:
Adam Jackson <ajax@redhat.com> Acked-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
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Keith Packard authored
Conflicts: drivers/gpu/drm/i915/intel_dp.c Just whitespace change conflicts
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- Oct 13, 2011
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Keith Packard authored
If the panel is powered up, there's no need to delay for the 'off' interval when turning the panel on. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
This eliminates a fairly long delay when power sequencing newer hardware Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- Oct 06, 2011
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Keith Packard authored
There's no good reason to turn off the eDP force VDD bit synchronously while probing devices; that just sticks a huge delay into all mode setting paths. Instead, queue a delayed work proc to disable the VDD force bit and then remember when that fires to ensure that the appropriate delay is respected before trying to turn it back on. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
We need to check eDP VDD force and panel on in several places, so create some simple helper functions to avoid duplicating code. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
The return value was unused, so just stop doing that. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
This value doesn't come directly from the VBT, and so is rather specific to the particular DP output. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Store the panel power sequencing delays in the dp private structure, rather than the global device structure. Who knows, maybe we'll get more than one eDP device in the future. From the eDP spec, we need the following numbers: T1 + T3 Power on to Aux Channel operation (panel_power_up_delay) This marks how long it takes the panel to boot up and get ready to receive aux channel communications. T8 Video signal to backlight on (backlight_on_delay) Once a valid video signal is being sent to the device, it can take a while before the panel is actuall showing useful data. This delay allows the panel to get something reasonable up before the backlight is turned on. T9 Backlight off to video off (backlight_off_delay) Turning the backlight off can take a moment, so this delay makes sure there is still valid video data on the screen. T10 Video off to power off (panel_power_down_delay) Presumably this delay allows the panel to perform an orderly shutdown of the display. T11 + T12 Power off to power on (panel_power_cycle_delay) So, once you turn the panel off, you have to wait a while before you can turn it back on. This delay is usually the longest in the entire sequence. Neither the VBIOS source code nor the hardware documentation has a clear mapping between the delay values they provide and those required by the eDP spec. The VBIOS code actually uses two different labels for the delay values in the five words of the relevant VBT table. **** MORE LATER *** Look at both the current hardware register settings and the VBT specified panel power sequencing timings. Use the maximum of the two delays, to make sure things work reliably. If there is no VBT data, then those values will be initialized to zero, so we'll just use the values as programmed in the hardware. Note that the BIOS just fetches delays from the VBT table to place in the hardware registers, so we should get the same values from both places, except for rounding. VBT doesn't provide any values for T1 or T2, so we'll always just use the hardware value for that. The panel power up delay is thus T1 + T2 + T3, which should be sufficient in all cases. The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy for T11, which isn't available anywhere. For the backlight delays, the eDP spec says T6 + T8 is the delay from the end of link training to backlight on and T9 is the delay from backlight off until video off. The hardware provides a 'backlight on' delay, which I'm taking to be T6 + T8 while the VBT provides something called 'T7', which I'm assuming is s On the macbook air I'm testing with, this yields a power-up delay of over 200ms and a power-down delay of over 600ms. It all works now, but we're frobbing these power controls several times during mode setting, making the whole process take an awfully long time. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Any call to intel_dp_sink_dpms must ensure that the panel has power so that the DP_SET_POWER operation will be correctly received. The only one missing this was in intel_dp_prepare. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
The DP i2c initialization code does a couple of i2c transactions, which means that an eDP panel must be powered up. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Talking to the eDP DDC channel requires that the panel be powered up. Wrap both the EDID and modes fetch code with calls to turn the vdd power on and back off. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
On eDP, DDC requires panel power, but turning that on uses the panel power sequencing timing values fetch from the DPCD data. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
If the panel is already off, we'll need to turn VDD on to execute the (useless) DPMS off code. Yes, it would be better to just not do any of this, but correctness, and *then* performance. Signed-off-by:
Keith Packard <keithp@keithp.com>
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- Oct 01, 2011
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Keith Packard authored
The VDD force bit is turned on before touching the panel, but if it was enabled, there was no call to turn it back off. Add a call. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
Cleans up code dealing with eDP a bit. Remove redundant checks in callers Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Avoid any question about locked registers by just writing the unlock pattern with every write to the register. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Verify that the eDP VDD is on, either with the panel being on or with the VDD force-on bit being set. This demonstrates that in many instances, VDD is not on when needed, which leads to failed EDID communications. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
We're going to assume that EDID is more reliable than the VBT tables for eDP panels, which is notably true on MacBook machines where the VBT contains completely bogus data. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
This masks out all interrupts and ack's any pending ones at IRQ uninstall time to make sure we don't receive any unexpected interrupts later on. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Keith Packard authored
We were relying on the BIOS to set these bits, which doesn't always happen. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- Sep 29, 2011
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Keith Packard authored
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Keith Packard authored
The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process. Also, re-initialize the refclk at resume time. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Keith Packard authored
When trying to use SSC on Ibex Peak without CK505, any non-SSC outputs (like VGA or TV) get broken. So, do not use SSC on Ibex Peak unless there is a CK505 available (as specified by the VBT). On Cougar Point, all clocking is internal, so SSC can always be used, and there will never be a CK505 available. This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. References: https://bugzilla.kernel.org/show_bug.cgi?id=21742 References: https://bugs.freedesktop.org/show_bug.cgi?id=38750 Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk>
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- Sep 28, 2011
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Keith Packard authored
The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of PCH/non-PCH eDP and LVDS). Disable SSC clocks when no panels are connected. Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk>
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Keith Packard authored
This includes whether an eDP panel is present, and whether that should use SSC (and at what frequency) Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
This tells the driver whether a CK505 clock source is available on pre-PCH hardware. If so, it should be used as the non-SSC source, leaving the internal clock for use as the SSC source. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Chris Wison <chris@chris-wilson.co.uk>
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Keith Packard authored
These are all KMS related anyways, so don't hide them under other debug levels. Signed-off-by:
Keith Packard <keithp@keithp.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk>
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- Sep 27, 2011
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Keith Packard authored
Signed-off-by:
Keith Packard <keithp@keithp.com>
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- Sep 22, 2011
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Keith Packard authored
Make the default FBC behaviour chipset specific, allowing us to turn it on by default for Ironlake and older where it has been seen to cause trouble with screen updates. Signed-off-by:
Keith Packard <keithp@keithp.com> Tested-by:
Francis Moreau <francis.moro@gmail.com>
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Simon Farnsworth authored
I was seeing a nasty 5 frame glitch every 10 seconds, caused by the poll for connection on DVI attached by SDVO. As my SDVO DVI supports hotplug detect interrupts, the fix is to enable them, and hook them in to the various bits of driver infrastructure so that they work reliably. Note that this is only tested on single-function DVI-D SDVOs, on two platforms (965GME and 945GSE), and has not been checked against a specification document. With lots of help from Adam Jackson <ajax@redhat.com> on IRC. Signed-off-by:
Simon Farnsworth <simon.farnsworth@onelan.co.uk> Reviewed-by:
Keith Packard <keithp@keithp.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Keith Packard authored
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Ben Widawsky authored
While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. I don't expect this code to make semaphores better or worse, but you never know... v2: Remove magic per Keith's suggestions. Ran Daniel's gem_ring_sync_loop test on this. v3: Ignored one of Keith's suggestions. v4: Removed some bloat per Daniel's recommendation. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Keith Packard <keithp@keithp.com> Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Wu Fengguang authored
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake, SandyBridge/CougarPoint and IvyBridge/PantherPoint chips. ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio capabilities of the plugged monitor. It's built and passed to audio driver in 2 steps: (1) at get_modes time, parse EDID and save ELD to drm_connector.eld[] (2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP. Test scheme: plug in the HDMI/DP monitor, and run cat /proc/asound/card0/eld* to check if the monitor name, HDMI/DP type, etc. show up correctly. Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always reads 0 (reserved). Without knowing the port number, I worked it around by setting the ELD_valid bit for ALL the three ports. It's tested to not be a problem, because the audio driver will find invalid ELD data and hence rightfully abort, even when it sees the ELD_valid indicator. Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing. CC: Zhao Yakui <yakui.zhao@intel.com> CC: Wang Zhenyu <zhenyu.z.wang@intel.com> CC: Jeremy Bush <contractfrombelow@gmail.com> CC: Christopher White <c.white@pulseforce.com> CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com> CC: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by:
Wu Fengguang <fengguang.wu@intel.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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Wu Fengguang authored
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio capabilities of the plugged monitor. This adds drm_edid_to_eld() for converting EDID to ELD. The converted ELD will be saved in a new drm_connector.eld[128] data field. This is necessary because the graphics driver will need to fixup some of the data fields (eg. HDMI/DP connection type, AV sync delay) before writing to the hardware ELD buffer. drm_av_sync_delay() will help the graphics drivers dynamically compute the AV sync delay for fixing-up the ELD. ELD selection policy: it's possible for one encoder to be associated with multiple connectors (ie. monitors), in which case the first found ELD will be returned by drm_select_eld(). This policy may not be suitable for all users, but let's start it simple first. The impact of ELD selection policy: assume there are two monitors, one supports stereo playback and the other has 8-channel output; cloned display mode is used, so that the two monitors are associated with the same internal encoder. If only the stereo playback capability is reported, the user won't be able to start 8-channel playback; if the 8-channel ELD is reported, then user space applications may send 8-channel samples down, however the user may actually be listening to the 2-channel monitor and not connecting speakers to the 8-channel monitor. According to James, many TVs will either refuse the display anything or pop-up an OSD warning whenever they receive hdmi audio which they cannot handle. Eventually we will require configurability and/or per-monitor audio control even when the video is cloned. CC: Zhao Yakui <yakui.zhao@intel.com> CC: Wang Zhenyu <zhenyu.z.wang@intel.com> CC: Jeremy Bush <contractfrombelow@gmail.com> CC: Christopher White <c.white@pulseforce.com> CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com> CC: Paul Menzel <paulepanter@users.sourceforge.net> CC: James Cloos <cloos@jhcloos.com> CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com> Signed-off-by:
Wu Fengguang <fengguang.wu@intel.com> Signed-off-by:
Keith Packard <keithp@keithp.com>
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