There is a further gate in between the mipidphy reference clock and the
actual ref-clock input to the dsi host, making the clock hirarchy look like
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll

Fix the clock reference so that the whole clock subtree gets enabled when
the dsi host needs it.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
[amended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This reverts commit 6f2dea1f

.

Without accurate cpu regulators being set for boards this will wreak havoc
when cpufreq-dt begins to set new frequencies without adjusting the core
frequency.

Additionally the rk3368 has an unsolved issue in that it has two separate
cpu clusters with separate clock lines but only one cpu supply regulator
for both clusters, which causes even more problems.

While it seems that originally only one cluster was supposed to be active
at a time (big or little), talking with real users of the hardware
revealed that having all 8 cores accessible at 1.2GHz max is way more
liked than having 4 cores at 1.5GHz max. Such an approach needs changes
to cpufreq and/or opp though to control the two separate clock lines when
setting both clusters to the same frequencies.

In any case, having the OPPs in the dts at this point in time is
undesireable, so remove them again for now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

"1" should be replaced by "l". This is a typo.
The patch is to fix it.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

The Armada AP806 has 20 pins, and therefore 20 GPIOs (from 0 to 19
included) and not 19 pins. Therefore, we fix the Device Tree
description for the GPIO controller.

Before this patch:

$ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges
GPIO ranges handled:
0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19]
0: f06f4000.system-controller:gpio GPIOS [0 - 18] PINS [0 - 18]

After this patch:

$ cat /sys/kernel/debug/pinctrl/f06f4000.system-controller:pinctrl/gpio-ranges
GPIO ranges handled:
0: mvebu-gpio GPIOS [0 - 19] PINS [0 - 19]
0: f06f4000.system-controller:gpio GPIOS [0 - 19] PINS [0 - 19]

Fixes: 63dac0f4

 ("arm64: dts: marvell: add gpio support for Armada 7K/8K")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This patch enables the two GE/SFP ports. They are configured in 10GKR
mode by default. To do this the cpm_xdmio is enabled as well, and two
phy descriptions are added.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The network driver on Marvell SoC (7k/8k) needs to access some registers
in the system controller to configure its ports at runtime. This patch
adds a phandle reference to the syscon system controller node in the
ppv2 node.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This commit updates the Marvell Armada 7K/8K Device Tree to describe
the TX interrupts of the Ethernet controllers, in both the master and
slave CP110s.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Convert all RK3399 platforms to use per-lane PHY model in order to save
more power by idling unused lane(s).

Tested-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>

Initial support for PXs3 SoC and its reference development board.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

All registers are located within 0x400 size from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Add UniPhier AIDET (ARM Interrupt Detector) nodes to support
active low interrupts.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Since the discussion is not settled yet for the EMAC, and that the release
in getting really close, let's revert the changes for now, and we'll
reintroduce them later.

Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

This patch adds reset controller node of analog signal amplifier
core (ADAMV) for UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Since i80/command mode is determined in runtime by propagating info
from panel this property can be removed.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>

This commit adds the base Device Tree files for the Armada 8KPlus.
The Armada 8KP SoCs include several hardware blocks, and this
commit only adds support for the AP810 block, that contains the CPU
core and basic peripherals.

AP810 is a high-performance die, includes octal core application
processor based ARMv8-A architecture, two standard high speed DDR4
interface, and GIC-600 interrupt controller.
AP810 Built as part of Marvell’s MoChi AP family products.

Armada-8080 (8KPlus family), include an AP810 block that contains
the CPU core and basic peripherals.

This commit creates the following hierarchy:
 * armada-ap810-ap0.dtsi - definitions common to AP810
 	* armada-ap810-ap0-octa-core.dtsi - description of the octa cores
		* armada-8080.dtsi - description of the 8080 SoC
			* armada-8080-db.dts - description of the 8080 board

Signed-off-by: Hanna Hawa <hannah@marvell.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Haikou is a Qseven and μQseven baseboard featuring PCIe, USB3 and a
video connector for MIPI-DSI/CSI and eDP adapter.

This dts is for usage with the RK3399-Q7 SoM Puma.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.

It provides the following feature set:
 * up to 4GB DDR3
 * on-module SPI-NOR flash
 * on-module eMMC (with 8-bit 1.8V interface)
 * SD card (on a baseboad) via edge connector
 * Gigabit Ethernet with on-module Micrel KSZ9031 GbE PHY
 * HDMI/eDP/2x MIPI-DSI
 * 2x MIPI-CSI
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
 * on-module STM32 Cortex-M0 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
   - USB<->CAN bridge controller

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The ROCK64 is a credit card size 4K60P HDR Media Board Computer using the
Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting
up to 4GB 1600MHz LPDDR3 memory. It provides eMMC module socket, MicroSD
Card slot, Pi-2 Bus, Pi-P5+ Bus, USB 3.0 and many others peripheral
devices interface for makers to integrate with sensors and devices.

The devicetree currently supports basic peripherals, with more to be
added later on.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch add pdm controller device node for rk3328.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

This patch describes the GPIO lines usage on the LibreTech CC board.

This is useful in the debugfs gpio file and using the cdev gpio API.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: minor whiespace fix]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

This patch adds the AO CEC node in all the HDMI enabled boards DTS.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

The AO clkc needs to be updated to new bindings with an system control parent
node and moving the clkc node as subnode.

Also adds the SoC specific compatible following the bindings requirements.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Add VPU/VDEC/IEP/ISP0/ISP1 iommu nodes

Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add IEP/ISP/VOP/HEVC/VPU iommu nodes

Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Add H265e/VEPU/VPU/VDEC/VOP iommu nodes

Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.

But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.

So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.

Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add missing mmc aliases.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This patch enables can1 for ep108.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Added clks for ep108 platform.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This enables option to use dt binding
headers.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Wire fpd and lpd dma channels to zynqmp.dtsi.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Do not enable smmu via dtsi. Enable it in board file when needed.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Mainline kernel has r1p12 compatible string now. Use this new compatible
string and also append generic compatible string.
Keep in your mind that using this generic compatible string not all uart
features will be available.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add support for RTC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Adding prefetchable memory space to pcie device tree node.
Shifting configuration space to 64-bit address space.
Removing pcie device tree node from amba as it requires size-cells=<2>
in order to access 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add CCI-400 node to DTSI.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add debug console to dtsi to be able to enable it in
board dts file.
Keep in your mind that every core has separate dcc port in case you want
to run SMP kernel.
DCC is very helpful communication channel for debugging.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>