- May 23, 2017
-
-
Kever Yang authored
Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Kever Yang authored
Add qos setting reg for some peripheral like sd, usb, pcie. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Mar 23, 2017
-
-
Shawn Lin authored
It's suggested to fix the domain number for all PCIe host bridges or not set it at all. However, if we don't fix it, the domain number will keep increasing ever when doing unbind/bind test, which makes the bus tree of lspci introduce pointless domain hierarchy. More investigation shows the domain number allocater of PCI doesn't consider the conflict of domain number if we have more than one PCIe port belonging to different domains. So once unbinding/binding one of them and keep others would going to overflow the domain number so that finally it will share the same domain as others, but actually it shouldn't. We should fix the domain number for PCIe or invent new indexing ID mechanisms. However it isn't worth inventing new indexing ID mechanisms personlly, Just look at how other Root Complex drivers did, for instance, broadcom and qualcomm, it seems fixing the domain number was more popular. So this patch gonna fix the domain number of PCIe for rk3399. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Mar 22, 2017
-
-
Heiko Stuebner authored
dw-mmc got its reset-properties specified, so add the softresets for it on the rk3399. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
-
Brian Norris authored
Add the dwc3 usb needed node information for rk3399. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Mar 06, 2017
-
-
Brian Norris authored
f8000000 is less than all the other (top-level) unit addresses. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jan 14, 2017
-
-
Xing Zheng authored
The structure rockchip_clk_provider needs to refer the GRF regmap in somewhere, if the CRU node has not "rockchip,grf" property, calling syscon_regmap_lookup_by_phandle will return an invalid GRF regmap, and the MUXGRF type clock will be not supported. Therefore, we need to add them. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jan 13, 2017
-
-
Shawn Lin authored
Per the discussion of bug fix[1], we now actually leaves the default clock choice for pcie phy is derived from 24MHz OSC to guarantee the least BER. So let's add aspm-no-l0s here and folks could delete this property from their dts. [1] https://patchwork.kernel.org/patch/9470519/ Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jan 06, 2017
-
-
Shawn Lin authored
Per the errata of TRM, rk3399 won't support gen2 from now on, so let's set max-link-speed to 1 in order not to doing training for gen2. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jan 02, 2017
-
-
William wu authored
We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. The root cause is that usb2-phy suspended earlier than ehci/ohci (usb2-phy will be auto suspended if no devices plug-in). and the clk-480m provided by it was disabled if no module used. However, some suspend process related ehci/ohci are base on this clock, so we should refer it into ehci/ohci driver to prevent this case. The u2phy clock flow like this: === u2phy ________________ | | |-----> UTMI_CLK ---------> | EHCI | OSC_24M ---|---> PHY_PLL----|----| |________^_______| |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC | | GRF === Signed-off-by: William wu <wulf@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Brian Norris authored
We haven't enabled eDP support yet, but we might as well describe the pin now. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Brian Norris authored
We're going to need to amend this table in board files. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 21, 2016
-
-
Brian Norris authored
The "arm,no-tick-in-suspend" property was introduced to note implementations where the system counter does not quite follow the ARM specification that it "must be implemented in an always-on power domain". Particularly, RK3399's counter stops ticking when we switch from the 24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as such. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-
- Nov 15, 2016
-
-
William Wu authored
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can be used for USB2.0 part of USB3.0 OTG controller. Signed-off-by: William Wu <wulf@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 14, 2016
-
-
Elaine Zhang authored
Add the sd power-domain, its qos area and assign it to the sdmmc device node. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Elaine Zhang authored
Control power domain for eMMC via genpd to reduce power consumption. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Jeffy Chen authored
This patch fixes that sometimes hang at start-up time of the system. As the below log: ... [ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1 [ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs [ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1 <hang> In some cases, the rk3399 should turn off the gmac power domain to save power if some boards didn't register the gmac device node for rk3399. Then, rk3399 need to make sure the gmac's pclk enabled if we need operate the gmac power domain. (Due to the NOC had enabled always) Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 11, 2016
-
-
Shawn Lin authored
pm_rst, aclk_rst and pclk_rst should be controlled by driver, so we need to add these three resets for PCIe controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 09, 2016
-
-
Jaehoon Chung authored
In drivers/mmc/core/host.c, there is "max-freqeuncy" property. It should be same behavior, So Use the "max-frequency" instead of "clock-freq-min-max". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Nov 02, 2016
-
-
Ziyuan Xu authored
There is a 'cpu-id' field in efuse, export it for other drivers reference. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Oct 16, 2016
-
-
Chris Zhong authored
The tcpc power domain will try to power up/down the power of Type-C PHY. Hence, we need control it in Type-C PHY driver with the pm_runtime helper. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Sep 08, 2016
-
-
Chris Zhong authored
There are 2 Type-C phy on RK3399, they are almost same, except the address of register. They support USB3.0 Type-C and DisplayPort1.3 Alt Mode on USB Type-C. Register a phy, supply it to USB3 controller and DP controller. Signed-off-by: Chris Zhong <zyw@rock-chips.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Roger Chen authored
The RK3399 GMAC Ethernet Controller provides a complete Ethernet interface from processor to a Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII) compliant Ethernet PHY. This patch adds the related needed device information. e.g.: interrupts, grf, clocks, pinctrl and so on. The full details are in [0]. [0]: Documentation/devicetree/bindings/net/rockchip-dwmac.txt Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Sep 06, 2016
-
-
Caesar Wang authored
This patch adds to enable the ARM Performance Monitor Units for rk3399. ARM cores often have a PMU for counting cpu and cache events like cache misses and hits. This uses the new interrupt-partition mechanism to allow the two pmu instances to use the per-cpu interrupt. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Caesar Wang authored
Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Sep 05, 2016
-
-
Caesar Wang authored
The tcpc is the Type C Port Controller and Type C Port Delivery (tcpd) is part of it, we haven't used them now, add it to save power consumption. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Sep 02, 2016
-
-
Finley Xiao authored
Add a efuse0 node in the device tree for the ARM64 rk3399 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Shawn Lin authored
This patch introduces PCIe support found on RK3399 platform, and specify phys phandle for it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Shawn Lin authored
This patch adds PCIe node for RK3399 to support PCIe controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Caesar Wang authored
This patch adds the gmac ppower-domain to save power consumption by letting the driver core handle the power-domain so we can save power on boards not needing Ethernet. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Douglas Anderson authored
On some rk3399 boards GPIO0_A0 is hooked up to a 32 kHz clock. This can be used as the source for various clocks in the system. Add a pinmux so boards can get this pin properly configured. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Aug 26, 2016
-
-
Shunqian Zheng authored
Per testing, this can reduce the memory latency and d8 gets better scores. Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Xing Zheng authored
Due to incorrect description in the TRM, the WDTs base address should be fixed and swap them like this: WDT0 - 0xff848000 WDT1 - 0xff840000 And, it is right that only WDT0 can generate global software reset. We will update the TRM to fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Aug 24, 2016
-
-
Caesar Wang authored
This patch adds saradc needed information on rk3399 SoCs. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Aug 17, 2016
-
-
Frank Wang authored
Add usb2-phy nodes and specify phys phandle for ehci. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Aug 08, 2016
-
-
Elaine Zhang authored
In order to meet low power requirements, a power management unit (PMU) is designed for controlling power resources in RK3399. The RK3399 PMU is dedicated for managing the power of the whole chip. 1. add pd node for RK3399 Soc 2. create power domain tree 3. add qos node for domain From the DT/binds and driver can get more detail information: The driver: drivers/soc/rockchip/pm_domains.c The document: Documentation/devicetree/bindings/soc/rockchip/power_domain.txt Note: As the TRM lists many voltage domains and power domains, then this patch adds some domains for driver. Due to some domains (e.g. emmc, usb, core)...We can't turned off it on bootup, or says some device driver can't handle the power domain enough. Maybe We will add more other domains in the future or later. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jun 28, 2016
-
-
Huang Tao authored
Add a 'rktimer' node in the device treee for the ARM64 rk3399 SoC. Signed-off-by: Huang Tao <huangtao@rock-chips.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Heiko Stuebner <heiko@sntech.de> Tested-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-
- Jun 27, 2016
-
-
Douglas Anderson authored
There are two sleep related pins on rk3399: ap_pwroff and ddrio_pwroff. Let's add the definition of these two pins to rk3399's main dtsi file so that boards can use them. These two pins are similar to the global_pwroff and ddrio_pwroff pins in rk3288 and are expected to be used in the same way: boards will likely want to configure these pinctrl settings in their global pinctrl hog list. Note that on rk3288 there were two additional pins in the "sleep" section: "ddr0_retention" and "ddr1_retention". On rk3288 designs these pins appeared to actually route from rk3288 back to rk3288. Presumably on rk3399 this is simply not needed since the pins don't appear to exist there. Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
- Jun 23, 2016
-
-
Douglas Anderson authored
Previous changes in this series allowed exposing the card clock from the rk3399 SDHCI device and allowed consuming the card clock in the rk3399 eMMC PHY. Hook things up in the main rk3399 dtsi file. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-
Douglas Anderson authored
On rk3399 we'd like to be able to properly set corecfg registers in the Arasan SDHCI component. Specify the syscon to enable that. Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-