- Apr 28, 2017
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Bjorn Helgaas authored
* pci/host-hv: PCI: hv: Convert hv_pci_dev.refs from atomic_t to refcount_t PCI: hv: Allocate interrupt descriptors with GFP_ATOMIC PCI: hv: Specify CPU_AFFINITY_ALL for MSI affinity when >= 32 CPUs PCI: hv: Lock PCI bus on device eject PCI: hv: Properly handle PCI bus remove
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Bjorn Helgaas authored
* pci/host-faraday: PCI: faraday: Add Faraday Technology FTPCI100 PCI Host Bridge driver PCI: Add DT bindings for Faraday Technology PCI Host Bridge
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Bjorn Helgaas authored
* pci/host-designware: ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP MAINTAINERS: Add PCI Endpoint maintainer Documentation: PCI: Add userguide for PCI endpoint test function tools: PCI: Add sample test script to invoke pcitest tools: PCI: Add a userspace tool to test PCI endpoint Documentation: misc-devices: Add Documentation for pci-endpoint-test driver misc: Add host side PCI driver for PCI test function device PCI: Add device IDs for DRA74x and DRA72x dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access PCI: dwc: dra7xx: Workaround for errata id i870 dt-bindings: PCI: dra7xx: Add DT bindings for PCI dra7xx EP mode PCI: dwc: dra7xx: Add EP mode support PCI: dwc: dra7xx: Facilitate wrapper and MSI interrupts to be enabled independently dt-bindings: PCI: Add DT bindings for PCI designware EP mode PCI: dwc: designware: Add EP mode support Documentation: PCI: Add binding documentation for pci-test endpoint function PCI: endpoint: functions: Add an EP function to test PCI Documentation: PCI: Add specification for the *PCI test* function device PCI: endpoint: Create configfs entry for EPC device and EPF driver Documentation: PCI: Guide to use PCI endpoint configfs PCI: endpoint: Introduce configfs entry for configuring EP functions Documentation: PCI: Guide to use PCI Endpoint Core Layer PCI: endpoint: Add EP core layer to enable EP controller and EP functions PCI: dwc: dra7xx: Push request_irq() call to the bottom of probe PCI: dwc: designware: Move _unroll configurations to a separate function PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes PCI: dwc: all: Modify dbi accessors to take dbi_base as argument PCI: dwc: artpec6: Populate cpu_addr_fixup ops PCI: dwc: dra7xx: Populate cpu_addr_fixup ops PCI: dwc: designware: Add new *ops* for CPU addr fixup PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq() PCI: dwc: Unindent dw_handle_msi_irq() loop PCI: dwc: Fix dw_pcie_ops NULL pointer dereference PCI: dwc: Select PCI_HOST_COMMON for hisi PCI: thunder-pem: Fix legacy firmware PEM-specific resources PCI: thunder-pem: Add legacy firmware support for Cavium ThunderX host controller PCI: thunder-pem: Use Cavium assigned hardware ID for ThunderX host controller PCI: iproc: Save host bridge window resource in struct iproc_pcie PCI/ASPM: Always set link->downstream to avoid NULL dereference on remove PCI: Prevent VPD access for QLogic ISP2722 PCI: exynos: Initialize elbi_base even when using PHY framework
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Kishon Vijay Abraham I authored
The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO in RC mode. However in EP mode, the host system is not able to access the MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it. Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add maintainer for the newly introduced PCI Endpoint framework. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add documentation to help users use pci-epf-test function driver and pci_endpoint_test host driver for testing PCI. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add a simple test script that invokes the pcitest userspace tool to perform all the PCI endpoint tests (BAR tests, interrupt tests, read tests, write tests and copy tests). Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add a userspace tool to invoke the ioctls exposed by the PCI endpoint test driver to perform various PCI tests. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add Documentation for pci-endpoint-test driver. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add PCI endpoint test driver that can verify base address register, legacy interrupt/MSI interrupt and read/write/copy buffers between host and device. The corresponding pci-epf-test function driver should be used on the EP side. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add device IDs for DRA74x and DRA72x devices. These devices have configurable PCI endpoint. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling unaligned mem access. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata here. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add device tree binding documentation for PCI dra7xx EP mode. Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
The PCIe controller integrated in dra7xx SoCs is capable of operating in endpoint mode. Add endpoint mode support to dra7xx driver. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
No functional change. Split dra7xx_pcie_enable_interrupts() into dra7xx_pcie_enable_wrapper_interrupts() and dra7xx_pcie_enable_msi_interrupts() so that wrapper interrupts and MSI interrupts can be enabled independently. This is in preparation for adding EP mode support to dra7xx driver since EP mode doesn't have to enable msi_interrupts. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add device tree binding documentation for PCI designware EP mode. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Rob Herring <robh@kernel.org>
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Kishon Vijay Abraham I authored
Add endpoint mode support to designware driver. This uses the EP Core layer introduced recently to add endpoint mode support. *Any* function driver can now use this designware device in order to achieve the EP functionality. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add binding documentation for pci-test endpoint function that helps in adding and configuring pci-test endpoint function. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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- Apr 18, 2017
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Elena Reshetova authored
refcount_t type and corresponding API should be used instead of atomic_t when the variable is used as a reference counter. This allows to avoid accidental refcounter overflows that might lead to use-after-free situations. Signed-off-by:
Elena Reshetova <elena.reshetova@intel.com> Signed-off-by:
Hans Liljestrand <ishkamiel@gmail.com> Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
David Windsor <dwindsor@gmail.com> Reviewed-by:
Stephen Hemminger <sthemmin@microsoft.com>
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- Apr 12, 2017
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Kishon Vijay Abraham I authored
Adds a new endpoint function driver (to program the virtual test device) making use of the EP-core library. [bhelgaas: fold in pci_epf_test_probe() -ENOMEM test from Wei Yongjun <weiyongjun1@huawei.com>] Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add specification for the *PCI test* virtual function device. The endpoint function driver and the host PCI driver should be created based on this specification. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Invoke APIs provided by pci-ep-cfs to create configfs entry for every EPC device and EPF driver to help users in creating EPF device and binding the EPF device to the EPC device. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add Documentation to help users use PCI endpoint to configure PCI endpoint function and to bind the endpoint function with endpoint controller. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-By:
Joao Pinto <jpinto@synopsys.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Introduce a new configfs entry to configure the EP function (like configuring the standard configuration header entries) and to bind the EP function with EP controller. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Add Documentation to help users use endpoint library to enable endpoint mode in the PCI controller and add new PCI endpoint functions. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-By:
Joao Pinto <jpinto@synopsys.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Introduce a new EP core layer in order to support endpoint functions in linux kernel. This comprises the EPC library (Endpoint Controller Library) and EPF library (Endpoint Function Library). EPC library implements functions specific to an endpoint controller and EPF library implements functions specific to an endpoint function. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Joao Pinto <jpinto@synopsys.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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- Apr 05, 2017
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K. Y. Srinivasan authored
The memory allocation here needs to be non-blocking. Fix the issue. Signed-off-by:
K. Y. Srinivasan <kys@microsoft.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Long Li <longli@microsoft.com> Cc: <stable@vger.kernel.org>
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K. Y. Srinivasan authored
When we have 32 or more CPUs in the affinity mask, we should use a special constant to specify that to the host. Fix this issue. Signed-off-by:
K. Y. Srinivasan <kys@microsoft.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
Long Li <longli@microsoft.com> Cc: <stable@vger.kernel.org>
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- Apr 04, 2017
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Keerthy authored
Currently devm_request_irq() is being called before base, PCI fields of dra7xx_pcie structure are populated. It is called even before pm_runtime_enable() and pm_runtime_get_sync() are called. This will lead to exceptions if in case an interrupt is triggered before the all of the above are done. Hence push the devm_request_irq() call to the end of the probe. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these functions are used to perform only outbound configurations. Also move these _unroll configurations to a separate function. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Kishon Vijay Abraham I authored
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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Kishon Vijay Abraham I authored
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper to access dbi address space can access only dbics. However dbics2 has to be accessed for programming the BAR registers in the case of EP mode. This is in preparation for adding EP mode support to dwc driver. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
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Kishon Vijay Abraham I authored
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Niklas Cassel <niklas.cassel@axis.com> Acked-by:
Joao Pinto <jpinto@synopsys.com>
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Kishon Vijay Abraham I authored
Populate cpu_addr_fixup ops to extract the least 28 bits of the corresponding CPU address. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Joao Pinto <jpinto@synopsys.com>
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Kishon Vijay Abraham I authored
Some platforms (like dra7xx) require only the least 28 bits of the corresponding 32 bit CPU address to be programmed in the address translation unit. This modified address is stored in io_base/mem_base/ cfg0_base/cfg1_base in dra7xx_pcie_host_init(). While this is okay for host mode where the address range is fixed, device mode requires different addresses to be programmed based on the host buffer address. Add a new ops to get the least 28 bits of the corresponding 32 bit CPU address and invoke it before programming the address translation unit. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Joao Pinto <jpinto@synopsys.com>
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Dan Carpenter authored
The bug is that "val" is unsigned long but we only initialize 32 bits of it. Then we test "if (val)" and that might be true not because we set the bits but because some were never initialized. Fixes: f342d940 ("PCI: exynos: Add support for MSI") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Bjorn Helgaas authored
Use "continue" to skip rest of the loop when possible to save an indent level. No functional change intended. Suggested-by:
walter harms <wharms@bfs.de> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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Niklas Cassel authored
Fix a crash from dereferencing a NULL dw_pcie_ops pointer. For example, on ARTPEC-6: Unable to handle kernel NULL pointer dereference at virtual address 00000004 pgd = c0204000 [00000004] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.11.0-rc3-next-20170321 #1 Hardware name: Axis ARTPEC-6 Platform task: db098000 task.stack: db096000 PC is at dw_pcie_writel_dbi+0x2c/0xd0 Prior to 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures"), every driver had a struct pcie_host_ops with function pointers, typically used as: if (pp->ops->readl_rc) return pp->ops->readl_rc(...); 442ec4c0 split struct pcie_host_ops into two pieces: struct dw_pcie_host_ops and struct dw_pcie_ops, so the above became: if (pci->ops->readl_dbi) return pci->ops->readl_dbi(...); But pcie-artpec6.c and pcie-designware-plat.c don't need the dw_pcie_ops pointers and didn't supply a pci->ops struct, which leads to NULL pointer dereferences. Supply an empty struct dw_pcie_ops to avoid the NULL pointer dereferences. [bhelgaas: changelog] Fixes: 442ec4c0 ("PCI: dwc: all: Split struct pcie_port into host-only and core structures") Signed-off-by:
Niklas Cassel <niklas.cassel@axis.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Acked-by:
Joao Pinto <jpinto@synopsys.com>
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Arnd Bergmann authored
Without PCI_HOST_COMMON support enabled, we get a link error: drivers/pci/dwc/built-in.o: In function `hisi_pcie_map_bus': pcie-hisi.c:(.text+0x8860): undefined reference to `pci_ecam_map_bus' drivers/pci/dwc/built-in.o: In function `hisi_pcie_almost_ecam_probe': pcie-hisi.c:(.text+0x88b4): undefined reference to `pci_host_common_probe' Add an explicit 'select', as the other users have. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Jingoo Han <jingoohan1@gmail.com>
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