- Reorder struct pci_dev to avoid holes and reduce size (Christophe
  JAILLET)

- Change pdev->rom_attr_enabled to single bit since it's only a boolean
  value (Christophe JAILLET)

- Use struct_size() in pirq_convert_irt_table() instead of hand-writing it
  (Christophe JAILLET)

- Explicitly include correct DT includes to untangle headers (Rob Herring)

- Fix a DOE race between destroy_work_on_stack() and the stack-allocated
  task->work struct going out of scope in pci_doe() (Ira Weiny)

- Use pci_dev_id() when possible instead of manually composing ID from
  dev->bus->number and dev->devfn (Xiongfeng Wang, Zheng Zengkai)

- Move pci_create_resource_files() declarations to linux/pci.h for alpha
  build warnings (Arnd Bergmann)

- Remove unused hotplug function declarations (Yue Haibing)

- Remove unused mvebu struct mvebu_pcie.busn (Pali Rohár)

- Unexport pcie_port_bus_type (Bjorn Helgaas)

- Remove unnecessary sysfs ID local variable initialization (Bjorn Helgaas)

- Fix BAR value printk formatting to accommodate 32-bit values (Bjorn
  Helgaas)

- Use consistent pointer types for config access syscall get_user() and
  put_user() uses (Bjorn Helgaas)

- Simplify AER_RECOVER_RING_SIZE definition (Bjorn Helgaas)

- Simplify pci_pio_to_address() (Bjorn Helgaas)

- Simplify pci_dev_driver() (Bjorn Helgaas)

- Fix pci_bus_resetable(), pci_slot_resetable() name typos (Bjorn Helgaas)

- Fix code and doc typos and code formatting (Bjorn Helgaas)

- Tidy config space save/restore messages (Bjorn Helgaas)

* pci/misc:
  PCI: Tidy config space save/restore messages
  PCI: Fix code formatting inconsistencies
  PCI: Fix typos in docs and comments
  PCI: Fix pci_bus_resetable(), pci_slot_resetable() name typos
  PCI: Simplify pci_dev_driver()
  PCI: Simplify pci_pio_to_address()
  PCI/AER: Simplify AER_RECOVER_RING_SIZE definition
  PCI: Use consistent put_user() pointer types
  PCI: Fix printk field formatting
  PCI: Remove unnecessary initializations
  PCI: Unexport pcie_port_bus_type
  PCI: mvebu: Remove unused busn member
  PCI: Remove unused function declarations
  PCI/sysfs: Move declarations to linux/pci.h
  PCI/P2PDMA: Use pci_dev_id() to simplify the code
  PCI/IOV: Use pci_dev_id() to simplify the code
  PCI/AER: Use pci_dev_id() to simplify the code
  PCI: apple: Use pci_dev_id() to simplify the code
  PCI/DOE: Fix destroy_work_on_stack() race
  PCI: Explicitly include correct DT includes
  x86/PCI: Use struct_size() in pirq_convert_irt_table()
  PCI: Change pdev->rom_attr_enabled to single bit
  PCI: Reorder pci_dev fields to reduce holes

- Add support for Switechtec PCIe Gen5 devices (Kelvin Cao)

* pci/controller/switchtec:
  PCI: switchtec: Add support for PCIe Gen5 devices
  PCI: switchtec: Use normal comment style

- Use Use devm_platform_get_and_ioremap_resource() instead of open-coding
  platform_get_resource() followed by devm_ioremap_resource() (Yang Li)

* pci/controller/resources:
  PCI: imx6: Use devm_platform_get_and_ioremap_resource()
  PCI: xgene-msi: Use devm_platform_get_and_ioremap_resource()
  PCI: v3: Use devm_platform_get_and_ioremap_resource()
  PCI: rcar-gen2: Use devm_platform_get_and_ioremap_resource()

- Add stubs for devm action functions that call clk_disable_unprepare() to
  avoid casts between incompatible function types (Krzysztof Wilczyński)

* pci/controller/remove-void-cast:
  PCI: microchip: Remove cast between incompatible function type
  PCI: keembay: Remove cast between incompatible function type
  PCI: meson: Remove cast between incompatible function type

- Fix disable of bridge windows during domain reset; previously we cleared
  the base/limit registers, which left the windows enabled (Nirmal Patel)

* pci/controller/vmd:
  PCI: vmd: Disable bridge window for domain reset

- Revert "PCI: tegra194: Enable support for 256 Byte payload" because Linux
  doesn't know how to reduce MPS from to 256 to 128 bytes for Endpoints
  below a Switch (because other devices below the Switch might already be
  operating), which leads to Malformed TLP errors (Vidya Sagar)

* pci/controller/tegra194:
  Revert "PCI: tegra194: Enable support for 256 Byte payload"

- Use 64-bit mask on MSI 64-bit PCI address to avoid zeroing out the upper
  32 bits (Rick Wertenbroek)

* pci/controller/rockchip:
  PCI: rockchip: Use 64-bit mask on MSI 64-bit PCI address

- Log unknown Qcom Endpoint IRQ events at error level, not debug level
  (Manivannan Sadhasivam)

- Add DT and driver support for qcom interconnect bandwidth voting for
  "pcie-mem" and "cpu-pcie" interconnects (Krishna chaitanya chundru)

* pci/controller/qcom-ep:
  PCI: qcom-ep: Add ICC bandwidth voting support
  dt-bindings: PCI: qcom: ep: Add interconnects path
  PCI: qcom-ep: Treat unknown IRQ events as an error

- Pass the Qcom Endpoint 4K alignment requirement for outbound windows to
  the EPF core so EPF drivers can use it (Manivannan Sadhasivam)

- Use alignment restriction from EPF core in Qcom EPF MHI driver
  (Manivannan Sadhasivam)

- Add Qcom Endpoint eDMA support by enabling the eDMA IRQ (Manivannan
  Sadhasivam)

- Add Qcom MHI eDMA support (Manivannan Sadhasivam)

- Add Qcom Snapdragon SM8450 support to the EPF MHI driver (Manivannan
  Sadhasivam)

- Use iATU for EPF MHI transfers smaller than 4K to avoid eDMA setup
  latency (Manivannan Sadhasivam)

- Add pci_epc_mem_init() kernel-doc (Manivannan Sadhasivam)

* pci/controller/qcom-edma:
  PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API
  PCI: epf-mhi: Use iATU for small transfers
  PCI: epf-mhi: Add support for SM8450
  PCI: epf-mhi: Add eDMA support
  PCI: qcom-ep: Add eDMA support
  PCI: epf-mhi: Make use of the alignment restriction from EPF core
  PCI: qcom-ep: Pass alignment restriction to the EPF core

- Configure controller so MHI bus master clock will be switched off while
  in ASPM L1.x states (Manivannan Sadhasivam)

- Add sa8775p DT binding and driver support (Mrinmay Sarkar)

- Fix broken DT SDX65 "compatible" property (Krzysztof Kozlowski)

* pci/controller/qcom:
  dt-bindings: PCI: qcom: Fix SDX65 compatible
  PCI: qcom: Add support for sa8775p SoC
  dt-bindings: PCI: qcom: Add sa8775p compatible
  PCI: qcom-ep: Switch MHI bus master clock off during L1SS

- Fix DED and SEC interrupt bit offsets so interrupt handlers work
  correctly (Daire McNamara)

- Make driver buildable as a module (Daire McNamara)

- Reorganize register #defines to align with hardware docs (Daire McNamara)

- Tweak register accessors to simplify callers (Daire McNamara)

- Refactor interrupt initialisation (Daire McNamara)

- Read FPGA MSI configuration parameters from hardware instead of
  hard-coding them (Daire McNamara)

- Re-partition code between probe() and init() (Daire McNamara)

* pci/controller/microchip:
  PCI: microchip: Re-partition code between probe() and init()
  PCI: microchip: Gather MSI information from hardware config registers
  PCI: microchip: Clean up initialisation of interrupts
  PCI: microchip: Enable event handlers to access bridge and control pointers
  PCI: microchip: Align register, offset, and mask names with HW docs
  PCI: microchip: Enable building driver as a module
  PCI: microchip: Correct the DED and SEC interrupt bit offsets

- Add support for link-down notification so the endpoint driver can process
  LINK_DOWN events (Frank Li)

- Save Link Capabilities during probe so they can be restored when handling
  a link-up event, since the controller loses the Link Width and Link Speed
  values during reset (Xiaowei Bao)

* pci/controller/layerscape:
  PCI: layerscape: Add workaround for lost link capabilities during reset
  PCI: layerscape: Add support for link-down notification

- Use of_property_read_bool() instead of low-level accessors for boolean
  properties (Rob Herring)

* pci/controller/iproc:
  PCI: iproc: Use of_property_read_bool() for boolean properties

- To avoid a NULL pointer dereference, skip MSI restore after hibernate if
  MSI/MSI-X hasn't been enabled (Dexuan Cui)

* pci/controller/hv:
  PCI: hv: Fix a crash in hv_pci_restore_msi_msg() during hibernation

- Set the supported number of MSI vectors so we can use all available MSI
  interrupts (Yong-Xuan Wang)

* pci/controller/fu740:
  PCI: fu740: Set the number of MSI vectors

- Add an imx6 .host_deinit() callback so we can clean up things like
  regulators on probe failure or driver unload (Mark Brown)

- Add PCIE_PME_TO_L2_TIMEOUT_US value for controller drivers that need to
  manually synchronize power removal (Frank Li)

- Add generic dwc suspend/resume APIs (dw_pcie_suspend_noirq() and
  dw_pcie_resume_noirq()) to be called by controller driver suspend/resume
  ops, and a controller callback to send PME_Turn_Off (Frank Li)

- Add layerscape suspend/resume support, including manual
  PME_Turn_off/PME_TO_Ack handshake (Hou Zhiqiang, Frank Li)

* pci/controller/dwc:
  PCI: layerscape: Add power management support for ls1028a
  PCI: dwc: Implement generic suspend/resume functionality
  PCI: Add PCIE_PME_TO_L2_TIMEOUT_US L2 ready timeout value
  PCI: dwc: Provide deinit callback for i.MX

- Assert PERST# when probing BCM2711 because some bootloaders don't do it
  (Jim Quinlan)

* pci/controller/brcmstb:
  PCI: brcmstb: Remove stale comment
  PCI: brcmstb: Assert PERST# on BCM2711

- Initialize pcie->nvecs (number of available MSIs) before use (Sven Peter)

* pci/controller/apple:
  PCI: apple: Initialize pcie->nvecs before use

- Ensure device is accessible before VPD access via sysfs (Alex Williamson)

- Ensure device doesn't go to a low-power state while we're polling for PME
  (Alex Williamson)

* pci/vpd:
  PCI: Fix runtime PM race with PME polling
  PCI/VPD: Add runtime power management to sysfs interface

- Correct parameter types for vga_str_to_iostate() and
  vga_update_device_decodes() (Sui Jingfeng)

- Simplify vga_arbiter_notify_clients() (Sui Jingfeng)

- Simplify vga_client_register() (Sui Jingfeng)

- Replace MIT license text with SPDX identifier (Sui Jingfeng)

- Fix lots of comment typos (Sui Jingfeng)

* pci/vga:
  PCI/VGA: Fix typos
  PCI/VGA: Replace full MIT license text with SPDX identifier
  PCI/VGA: Simplify vga_client_register()
  PCI/VGA: Simplify vga_arbiter_notify_clients()
  PCI/VGA: Correct vga_update_device_decodes() parameter type
  PCI/VGA: Correct vga_str_to_iostate() io_state parameter type

- Avoid bus resets on NVIDIA T4 GPUs because they don't seem to recover (Wu
  Zongyong)

* pci/virtualization:
  PCI: Mark NVIDIA T4 GPUs to avoid bus reset

- Only read PCI_PM_CTRL register when available, to avoid reading the wrong
  register and corrupting dev->current_state (Feiyang Chen)

* pci/pm:
  PCI/PM: Only read PCI_PM_CTRL register when available

- Add locking for read/modify/write PCIe Capability Register accessors for
  Link Control and Root Control (Ilpo Järvinen)

- Use PCIe RMW accessors for Link Control updates in PCI core, pciehp,
  amdgpu, radeon, mlx5, ath10k, ath11k, ath12k (Ilpo Järvinen)

- Convert PCIBIOS error values in mlx5 to generic errnos (Ilpo Järvinen)

- Simplify pcie_capability_clear_and_set_word() control flow (Bjorn
  Helgaas)

* pci/pcie-rmw:
  PCI: Simplify pcie_capability_clear_and_set_word() control flow
  net/mlx5: Convert PCI error values to generic errnos
  PCI: Document the Capability accessor RMW improvements
  wifi: ath10k: Use RMW accessors for changing LNKCTL
  wifi: ath12k: Use RMW accessors for changing LNKCTL
  wifi: ath11k: Use RMW accessors for changing LNKCTL
  net/mlx5: Use RMW accessors for changing LNKCTL
  drm/radeon: Use RMW accessors for changing LNKCTL
  drm/amdgpu: Use RMW accessors for changing LNKCTL
  PCI/ASPM: Use RMW accessors for changing LNKCTL
  PCI: pciehp: Use RMW accessors for changing LNKCTL
  PCI: Make link retraining use RMW accessors for changing LNKCTL
  PCI: Add locking to RMW PCI Express Capability Register accessors

- Make I/O resources depend on CONFIG_HAS_IOPORT so inw() and friends can
  be completely omitted on architectures without I/O port support (Niklas
  Schnelle)

* pci/ioport:
  PCI/sysfs: Make I/O resource depend on HAS_IOPORT
  PCI: Make quirk using inw() depend on HAS_IOPORT

- Make ibmphp read-only arrays static instead of putting them on the stack
  (Colin Ian King)

* pci/hotplug:
  PCI: ibmphp: Make read-only arrays static

- Remove pci_disable_pcie_error_reporting() (unused) and unexport
  pci_enable_pcie_error_reporting().  This all done by the PCI core now
  (Bjorn Helgaas)

* pci/aer:
  PCI/AER: Unexport pci_enable_pcie_error_reporting()
  PCI/AER: Drop unused pci_disable_pcie_error_reporting()

Add support for voting interconnect (ICC) bandwidth based
on the link speed and width.

This commit is inspired from the basic interconnect support added
to pcie-qcom driver in commit c4860af8 ("PCI: qcom: Add basic
interconnect support").

The interconnect support is kept optional to be backward compatible
with legacy device trees.

[kwilczynski: add missing kernel-doc for the icc_mem variable]
Link: https://lore.kernel.org/linux-pci/1689751218-24492-5-git-send-email-quic_krichai@quicinc.com


Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Some platforms may not boot if a device driver doesn't
initialize the interconnect path. Mostly it is handled
by the bootloader but we have starting to see cases
where bootloader simply ignores them.

Add the "pcie-mem" & "cpu-pcie" interconnect path as a required
property to the bindings.

Link: https://lore.kernel.org/linux-pci/1689751218-24492-2-git-send-email-quic_krichai@quicinc.com


Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Sometimes, the Qcom PCIe EP controller can receive some interrupts
unknown to the driver, like safety interrupts in newer SoCs. In those
cases, if the driver doesn't clear the interrupts, it will end up in an
interrupt storm. However, the users will not know about it because the
log is treated as a debug message.

So let's treat the unknown event log as an error so that it at least
makes the user aware, thereby getting fixed eventually.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230726152931.18134-1-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Commit c0aba9f3 ("dt-bindings: PCI: qcom: Add SDX65 SoC") adding
SDX65 was never tested and is clearly bogus.  The qcom,sdx65-pcie-ep
compatible is followed by a fallback in DTS, and there is no driver
matched by this compatible.  Driver matches by its fallback
qcom,sdx55-pcie-ep.  This also fixes dtbs_check warnings like:

  qcom-sdx65-mtp.dtb: pcie-ep@1c00000: compatible: ['qcom,sdx65-pcie-ep', 'qcom,sdx55-pcie-ep'] is too long

[kwilczynski: commit log]
Fixes: c0aba9f3 ("dt-bindings: PCI: qcom: Add SDX65 SoC")
Link: https://lore.kernel.org/linux-pci/20230827085351.21932-1-krzysztof.kozlowski@linaro.org


Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Cc: stable@vger.kernel.org

Add missing kernel-doc for pci_epc_mem_init() API.

Link: https://lore.kernel.org/linux-pci/20230717065459.14138-8-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>

For transfers below 4K, let's use iATU since using eDMA for such small
transfers is inefficient.

This is mainly because setting up an eDMA transfer and waiting for
completion adds some latency. This latency is negligible for large
transfers but not for the smaller ones.

With using iATU, there is an increase in ~50Mbps throughput on both MHI
UL (Uplink) and DL (Downlink) channels.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230717065459.14138-7-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Add support for Qualcomm Snapdragon SM8450 SoC to the EPF driver. SM8450
has the dedicated PID (0x0306) and supports eDMA. Currently, it has no
fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS".

Link: https://lore.kernel.org/linux-pci/20230717065459.14138-6-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Add support for Embedded DMA (eDMA) available in the DesignWare PCIe IP
to transfer the MHI buffers between the host and the endpoint. The eDMA
use helps achieve greater throughput as the transfers are offloaded from
CPUs.

For differentiating the iATU and eDMA APIs, the pci_epf_mhi_{read/write}
APIs are renamed to pci_epf_mhi_iatu_{read/write} and separate eDMA
specific APIs pci_epf_mhi_edma_{read/write} are introduced.

Platforms that require eDMA support can pass the MHI_EPF_USE_DMA flag
through pci_epf_mhi_ep_info.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230717065459.14138-5-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA)
peripheral for offloading the data transfer between the PCIe bus and
memory.

Let's add support for it by enabling the eDMA IRQ in the driver. The
eDMA DMA Engine driver will handle the rest of the functionality.

Since the eDMA on Qualcomm platforms only uses a single IRQ for all
channels, use 1 for edma.nr_irqs.

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230717065459.14138-4-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

Instead of hardcoding the alignment restriction in the EPF_MHI driver, make
use of the info available from the EPF core that reflects the alignment
restriction of the endpoint controller.

For this purpose, let's introduce the get_align_offset() static function.

[kwilczynski: update get_align_offset() to avoid issues on 32-bit architectures]
Link: https://lore.kernel.org/linux-pci/20230717065459.14138-3-manivannan.sadhasivam@linaro.org
Link: https://lore.kernel.org/linux-pci/20230826150626.23309-1-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>

For a device with no Power Management Capability, pci_power_up() previously
returned 0 (success) if the platform was able to put the device in D0,
which led to pci_set_full_power_state() trying to read PCI_PM_CTRL, even
though it doesn't exist.

Since dev->pm_cap == 0 in this case, pci_set_full_power_state() actually
read the wrong register, interpreted it as PCI_PM_CTRL, and corrupted
dev->current_state.  This led to messages like this in some cases:

  pci 0000:01:00.0: Refused to change power state from D3hot to D0

To prevent this, make pci_power_up() always return a negative failure code
if the device lacks a Power Management Capability, even if non-PCI platform
power management has been able to put the device in D0.  The failure will
prevent pci_set_full_power_state() from trying to access PCI_PM_CTRL.

Fixes: e200904b ("PCI/PM: Split pci_power_up()")
Link: https://lore.kernel.org/r/20230824013738.1894965-1-chenfeiyang@loongson.cn


Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: stable@vger.kernel.org	# v5.19+

Add support for sa8775p SoC that uses controller version 5.90
reusing the 1.9.0 config.

Link: https://lore.kernel.org/linux-pci/1689960276-29266-3-git-send-email-quic_msarkar@quicinc.com


Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

Add sa8775p platform to the binding.

Link: https://lore.kernel.org/linux-pci/1689960276-29266-2-git-send-email-quic_msarkar@quicinc.com


Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>

Qcom PCIe EP controllers have 4K alignment restriction for the outbound
window address. Hence, pass this info to the EPF core so that the EPF
drivers can make use of this info.

Link: https://lore.kernel.org/linux-pci/20230717065459.14138-2-manivannan.sadhasivam@linaro.org


Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>