- Mar 12, 2018
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Shunqian Zheng authored
The ACLK_VIO is a parent clock used by a several children, its suggested clock rate is 400MHz. Right now it gets 400MHz because it sources from CPLL(800M) and divides by 2 after reset. It's good not to rely on default values like this, so let's explicitly set it. NOTE: it's expected that at least one board may override cru node and set the CPLL to 1.6 GHz. On that board it will be very important to be explicit about aclk-vio being 400 MHz. Signed-off-by:
Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 20, 2018
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Heiko Stuebner authored
While the sapphire board is a system-on-module and mostly used with the excavator baseboard, it is also possible to use it standalone without any base. So add a board-variant for this type. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Vicente Bergas <vicencb@gmail.com> Reviewed-by:
Rob Herring <robh@kernel.org>
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Vicente Bergas authored
The power button is located on the daughterboard. Signed-off-by:
Vicente Bergas <vicencb@gmail.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Vicente Bergas authored
The i2s2 drives the HDMI audio, which has the connector on the daughterboard. Signed-off-by:
Vicente Bergas <vicencb@gmail.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Heiko Stuebner authored
The sdio signals are routed through the connector to the baseboard, where the wifi module is also located. So move the sdio node to the excavator as well. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Vicente Bergas <vicencb@gmail.com>
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- Feb 19, 2018
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Klaus Goger authored
Enable the NXP SGTL5000 audio codec on the RK3399-Q7 EVK baseboard Haikou. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
The I2S definition is part of the SoM and therefore should be in rk3399-puma.dtsi. Also correct the number of channels available. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Vicente Bergas authored
The vdd_log power supply is controlled by a PWM pin, not by i2c register access. There is a boot message that reports an error about not being able to bring that supply up. Signed-off-by:
Vicente Bergas <vicencb@gmail.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 17, 2018
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Klaus Goger authored
Haikou is a Qseven and μQseven baseboard used in Theobroma Systems evaluation kits. This dts adds a version for use with a RK3368-uQ7 SoM called Lion. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
The RK3368-uQ7 SoM is a uQseven-compatible (40mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3368. It provides the following feature set: * up to 4GB DDR3 * on-module SPI-NOR flash * on-module eMMC (with 8-bit 1.8V interface) * SD card (on a baseboad) via edge connector * Gigabit Ethernet with on-module Micrel KSZ9031 GbE PHY * HDMI/eDP/MIPI-DSI/LVDS * MIPI-CSI * USB - 1x USB 2.0 dual-role - 1x USB 2.0 host * on-module STM32 Cortex-M0 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) - USB<->CAN bridge controller Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 16, 2018
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Robin Murphy authored
Using a serial console on RK3328 provokes an error from of_dma_request_slave_channel() since the UART nodes have a "dmas" property but are missing the mandatory "dma-names" to go with it. Replace the bogus "#dma-cells" - these UARTs are DMA channel consumers, not providers - with the appropriate names instead. DMA still doesn't actually work, since the PL330 driver doesn't quite implement everything the 8250 driver demands, but at least it makes the DT correct. Signed-off-by:
Robin Murphy <robin.murphy@arm.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 14, 2018
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Chris Zhong authored
Enable cdn_dp and create a cdn-dp-sound for the DP audio. Delete the endpoints between dp and vopL for gru, since we want the DP only use VOP big, which can support 4K mode. Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> [dropped vop-hacks] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Chris Zhong authored
Add a node for the cdn DP controller which is embedded in the rk3399 SoC. Signed-off-by:
Chris Zhong <zyw@rock-chips.com> Signed-off-by:
Enric Balletbo i Serra <enric.balletbo@collabora.com> [fixed whitespaces instead of tabs, dropped unnecessary address+size-cells and fixed the number of interrupt cells] Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Feb 12, 2018
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Klaus Goger authored
Add pin definition for I2S0 if used as a 2-channel only bus. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Klaus Goger authored
Enable the SoC thermal sensor on RK3399-Q7 (Puma). As we want to do do a full board reset instead of just a SoC one, set hw-tshut-mode to GPIO. Signed-off-by:
Klaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Levin Du authored
The roc-rk3328-cc is a credit card size single board computer using the Rockchip RK3328 Quad-Core ARM Cortex A53 64-Bit Processor and supporting up to 2GB 2133MHz LPDDR4 memory. It provides eMMC module socket, MicroSD Card slot, USB 2.0/3.0, Gigabit Ethernet, HDMI/CVBS, Infrared Receiver, SPDIF/I2S, and SPI/I2C/UART/PWM interfaces. The devicetree currently supports basic peripherals. Signed-off-by:
Levin Du <djw@t-chip.com.cn> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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Shunqian Zheng authored
There are three pins can act as cif test clock for rk3399. They're sourced from 24M and output 24M by default and some boards may use them as camera 24M xvclk. Signed-off-by:
Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-by:
Brian Norris <briannorris@chromium.org> Signed-off-by:
Heiko Stuebner <heiko@sntech.de>
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- Jan 23, 2018
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Thor Thayer authored
Correct the SPI Master node settings. Signed-off-by:
Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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Dinh Nguyen authored
The USB IP on the Stratix10 SoC needs the USB OCP(ecc) bit to get de-asserted as well for the USB IP to work properly. Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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Dinh Nguyen authored
Enable USB on the Stratix10 devkit. Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org>
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- Jan 13, 2018
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Gregory CLEMENT authored
When replacing the cpm by cp0 and cps by cp1 [1] not only the label and the alias were replaced but also the compatible string which was wrong. Due to this the pinctrl driver was no more probed. This patch fix it by reverting this change for the pinctrl compatible string on Armada 8K. [1]: "arm64: dts: marvell: replace cpm by cp0, cps by cp1" Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Jan 12, 2018
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Arnd Bergmann authored
dtc complains about the lack of #coolin-cells properties for the CPU nodes that are referred to as "cooling-device": arch/arm64/boot/dts/mediatek/mt8173-evb.dtb: Warning (cooling_device_property): Missing property '#cooling-cells' in node /cpus/cpu@0 or bad phandle (referred from /thermal-zones/cpu_thermal/cooling-maps/map@0:cooling-device[0]) arch/arm64/boot/dts/mediatek/mt8173-evb.dtb: Warning (cooling_device_property): Missing property '#cooling-cells' in node /cpus/cpu@100 or bad phandle (referred from /thermal-zones/cpu_thermal/cooling-maps/map@1:cooling-device[0]) Apparently this property must be '<2>' to match the binding. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Tested-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Arnd Bergmann authored
The PMU node has no working interrupt, as shown by this dtc warning: arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dtb: Warning (interrupts_property): Missing interrupt-parent for /pmu This adds an interrupt-parent property so we can correct parse that interrupt number. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
Dinh Nguyen <dinguyen@kernel.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Jan 09, 2018
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Chunfeng Yun authored
Use new binding about USB wakeup which now supports multi USB wakeup glue layer between SSUSB and SPM. Meanwhile remove dummy clocks of USB wakeup. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Jan 06, 2018
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Yixun Lan authored
This is tested in the S400 dev board which use a RTL8211F PHY, and the pins connect to the 'eth_rgmii_y_pins' group. Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Yixun Lan authored
Add DT info for the stmmac ethernet MAC which found in the Amlogic's Meson-AXG SoC, also describe the ethernet pinctrl & clock information here. Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Sunny Luo authored
Add DT info for the SPICC controller which found in the Amlogic's Meson-AXG SoC. Signed-off-by:
Sunny Luo <sunny.luo@amlogic.com> Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Yixun Lan authored
Enable IR remote controller which found in Amlogic's Meson-AXG SoCs. Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Yixun Lan authored
Switch the uart_ao pclk to CLK81 since the clock driver is ready. Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com>
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Yan Markman authored
This patch adds Ethernet aliases in the Marvell Armada 7040 DB, 8040 DB and 8040 mcbin device trees so that the bootloader setup the MAC addresses correctly. Signed-off-by:
Yan Markman <ymarkman@marvell.com> [Antoine: commit message, small fixes] Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
In preparation for the introduction of more than 2 CPs in upcoming SoCs, it makes sense to move away from the "CP master" (cpm) and "CP slave" (cps) naming, and use instead cp0/cp1. This commit is the result of: sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/* sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/* So it is a purely mechaninal change. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by:
Hanna Hawa <hannah@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
One concept of Marvell Armada 7K/8K SoCs is that they are made of HW blocks composed of a variety of IPs (network, PCIe, SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated several times within a given SoC. The Armada 7K SoC has a single CP110 (so no duplication), while the Armada 8K SoC has two CP110. In the future, SoCs with more than 2 CP110s will be introduced. In current kernel versions, the master CP110 is described in armada-cp110-master.dtsi and the slave CP110 is described in armada-cp110-slave.dtsi. Those files are basically exactly the same, since they describe the same hardware. They only have a few differences: - Base address of the registers is different for the "config-space" - Base address of the PCIe registers, MEM, CONF and IO areas were different - Labels (and phandles pointing to them) of the nodes were different ("cpm" prefix in the master CP, "cps" prefix in the slave CP) This duplication issue has been discussed at the DT workshop [1] in Prague last October, and we presented on this topic [2]. The solution of using the C pre-processor to avoid this duplication has been validated by the people present in this DT workshop, and this patch simply implements what has been presented. We handle differences between the master CP and slave CP description using the C pre-processor, by defining a set of macros with different values armada-cp110.dtsi is included to instantiate one of the master or slave CP110. There are a few aspects that deserve additional explanations: - PCIe needs to be handled separately because it is not part of the config-space {...} node, since it has registers outside of the range covered by config-space {...}. - We need to defined CP110_BASE, CP110_PCIEx_BASE without 0x, because they are used for the unit address part of some DT nodes. But since they are also used for the "reg" property of the same nodes, we have an ADDRESSIFY() macro that prepends 0x to those values. We compared the resulting .dtb for armada-8040-db.dtb before and after this patch is applied, and the result is exactly the same, except for a few differences: - the SDHCI controller that was only described in the master CP110 is now also described in the slave CP110. Even though the SDHCI controller from the slave CP110 is indeed not usable (as it isn't wired to the outside world) it is technically part of the silicon, and therefore it is reasonable to also describe it to be part of the slave CP110. In addition, if we wanted to get this correct for the SDHCI controller, we should also do it for the NAND controller, for which the situation is even more complicated: in a single CP110 configuration (Armada 7K), the usable NAND controller is in the master CP110, while in a dual CP110 configuration (Armada 8K), the usable NAND controller is in the slave CP110. Since that would add a lot of additional complexity for no good reason, and since the IP blocks are in fact really present in both CPs, we simply describe them in both CPs at the DT level. - the cp110-master and cp110-slave nodes are now named cpm and cps. We could have kept cp110-master and cp110-slave, but that would have required adding another CP110_xyz define, which didn't seem very useful. Note that this commit also gets rid of the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, as future SoCs will have more than 2 CPs. Instead, we instantiate the CPs directly from the SoC-specific .dtsi files, i.e armada-70x0.dtsi and armada-80x0.dtsi. [1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad [2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf [gregory.clement@free-electrons.com: add back the "ARM64: dts: marvell: Fix clock resources for various node" commit] Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
We are currently using the cell-index DT property to assign SPI bus numbers. This property is specific to the spi-orion driver, and requires each SPI controller to have a unique ID defined in the Device Tree. As we are about to merge armada-cp110-master.dtsi and armada-cp110-slave.dtsi into a single file, those cell-index properties that differ between the master CP110 and the slave CP110 are a difference that would have to be handled. In order to avoid this, we switch to using the "aliases" DT node to assign a unique number to each SPI controller. This is more generic, and directly handled by the SPI core. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
Back when the ICU Device Tree binding was introduced, we could not use mvebu-icu.h from the Device Tree files, because the DT files and mvebu-icu.h were following different merge routes towards Linus tree. Now that both have been merged, we can switch the Marvell Armada CP110 Device Tree files to use the mvebu-icu.h header instead of duplicating the ICU_GRP_NSR definition. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
The Armada CP110 slave NAND controller Device Tree description lists the compatible string in the wrong order: marvell,armada-8k-nand should come first. This commit alignes the slave CP110 description with the master CP110 description from that respect. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
Fix the same typo duplicated in both master and slave version of armada-cp110-*.dtsi file: s/limiation/limitation/. [gregory.clement@free-electrons.com: add the commit log] Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
This fixes the following DTC warning: <stdout>: Warning (simple_bus_reg): Node /ap806/config-space@f0000000/thermal@6f808C simple-bus unit address format error, expected "6f808c" Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
This fixes the following DTC warning: Warning (simple_bus_reg): Node /ap806/config-space@f0000000/watchdog@600000 simple-bus unit address format error, expected "610000" Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
This patch adds a crypto node describing the EIP97 engine found in Armada 37xx SoCs. The cryptographic engine is enabled by default. Signed-off-by:
Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Jan 05, 2018
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Gregory CLEMENT authored
On the CP modules we found on Armada 7K/8K, many IP block actually also need a "functional" clock (from the bus). This patch add them which allows to fix some issues hanging the kernel: If Ethernet and sdhci driver are built as modules and sdhci was loaded first then the kernel hang. Fixes: bb16ea17 ("mmc: sdhci-xenon: Fix clock resource by adding an optional bus clock") Cc: stable@vger.kernel.org Reported-by:
Riku Voipio <riku.voipio@linaro.org> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
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