- Jun 16, 2013
-
-
Haojian Zhuang authored
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Haojian Zhuang authored
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Haojian Zhuang authored
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Soren Brinkmann authored
A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- Jun 12, 2013
-
-
Stephen Warren authored
Modify the drivers/clk MAINTAINERS entry so that it matches the entire drivers/clk tree, with the exception of clkdev.c which has a separate entry. Make a similar change to pick up all clk-related header files. This causes get_maintainers.pl to spit out the expected results for any patches to clock drivers that are in sub-directories of drivers/clk, e.g. drivers/clk/tegra/. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by:
Mark Zhang <markz@nvidia.com> Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE is set. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
Define override bits for Tegra30 PLLM. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
Define override bits for Tegra114 PLLM. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
-
Peter De Schrijver authored
PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
Use the correct parents for sclk according to the TRM. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
The m,n,p fields don't have the same bit offset and width across all PLLs. This patch allows SoC specific files to indicate the offset and width. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Peter De Schrijver authored
The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by:
Stephen Warren <swarren@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- Jun 11, 2013
-
-
Shawn Guo authored
If the current rate of parent clock is sufficient to provide child a requested rate with a proper divider setting, the rate change request should not be propagated. Instead, changing the divider setting is good enough to get child clock run at the requested rate. On an imx6q clock configuration illustrated below, ahb --> ipg --> ipg_per 132M 66M 66M calling clk_set_rate(ipg_per, 22M) with the current clk_divider_bestdiv() implementation will result in the rate change up to ahb level like the following, because of the unnecessary/incorrect rate change propagation. ahb --> ipg --> ipg_per 66M 22M 22M Fix the problem by trying to see if the requested rate can be achieved by simply changing the divider value, and in that case return the divider immediately from function clk_divider_bestdiv() as the best one, so that all those unnecessary rate change propagation can be saved. Reported-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- Jun 07, 2013
-
-
Philippe Begnic authored
First clocks definition version of PRCMU and PRCC clocks for u8540 platform Signed-off-by:
Philippe Begnic <philippe.begnic@st.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Philippe Begnic authored
BML clock register address in DB8580 has changed.Defined a new address under different name for DB8580. Signed-off-by:
Philippe Begnic <philippe.begnic@st.com> Acked-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Philippe Begnic authored
PRCMU and ab8500 registers updated for u8540 Signed-off-by:
Philippe Begnic <philippe.begnic@st.com> Acked-by:
Lee Jones <lee.jones@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Philippe Begnic authored
Align on u8500 version, pass clock base address in clk_init functions for u8540 and u9540. Signed-off-by:
Linus Walleij <linus.walleij@stericsson.com> Signed-off-by:
Philippe Begnic <philippe.begnic@st.com> Reviewed-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- Jun 05, 2013
-
-
Mikko Perttunen authored
The msenc clock's register was set to the usb3 clock's register. Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Acked-by:
Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- Jun 01, 2013
-
-
Prashant Gaikwad authored
Use common of_clk_init() function for clocks initialization. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by:
Thierry Reding <thierry.reding@gmail.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Alexandre Courbot authored
Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Prashant Gaikwad authored
Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by:
Thierry Reding <thierry.reding@gmail.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Daniel Tang authored
This patch adds a basic clock driver for the TI-Nspire calculator series. Changes from v1: * Removed filename in header comment * Removed unnecessary #undef EXTRACT statement Signed-off-by:
Daniel Tang <dt.tangr@gmail.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT and changelog max width]
-
- May 31, 2013
-
-
Jingoo Han authored
Use the wrapper functions for getting and setting the driver data using platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, so we can directly pass a struct platform_device. Signed-off-by:
Jingoo Han <jg1.han@samsung.com> Acked-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Tang Yuantian authored
The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by:
Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
-
- May 30, 2013
-
-
Giacomo A. Catenazzi authored
In some architectures, the #define cpu_data is not a "macro-function", so the compiler will substitute the identifier with probably something wrong. Signed-off-by:
Giacomo A. Catenazzi <cate@cateee.net> Signed-off-by:
Emilio López <emilio@elopez.com.ar> [emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data] Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Tushar Behera authored
'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Tushar Behera authored
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Tony Prisk authored
The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by:
Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Tony Prisk authored
The WM8850 has a different PLL clock to the previous versions. This patch adds support for the WM8850-style PLL clocks. Signed-off-by:
Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
- May 29, 2013
-
-
Saravana Kannan authored
With deferred probing, late_initcall() is too soon to declare a clock as unused. Wait for deferred probing to finish before declaring a clock as unused. Since deferred probing is done in late_initcall(), do the unused check to late_initcall_sync. Signed-off-by:
Saravana Kannan <skannan@codeaurora.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Axel Lin authored
Current code looks strange because calling wm831x_clkout_set_parent() with 0 as parent parameter, wm831x_clkout_get_parent() will return 1. According to the datasheet: R16528 (4090h) Clock Control1 BIT 0: CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Thus fix the entry order in wm831x_clkout_parents[] to make it has the same meaning as the datasheet and make the return value of wm831x_clkout_get_parent() consistent with the parent pass to wm831x_clkout_set_parent(). Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Axel Lin authored
According to the datasheet, FLL Enable is controlled by R16530 (4092h) FLL Control1 BIT 0: FLL Enable 0 = Disable 1 = Enable Thus the code should update WM831X_FLL_CONTROL_1 register rather than WM831X_FLL_CONTROL_2 register. Also fixes a trivial typo in dev_crit message. Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Sebastian Hesselbarth authored
With of_clk_provider stubs for CONFIG_OF not set, we can now also enable clk-si5351 on those architectures. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Sebastian Hesselbarth authored
Some drivers that are shared between architectures have HAVE_CLK selected but don't have OF. To remove compilation errors for drivers that provide clocks on DT with of_clk_add_provider we would have to enclose these calls within #ifdef CONFIG_OF, #endif. This patch adds some stubs for OF related clk-provider functions that either do nothing or return appropriate values if CONFIG_OF is not set. So, definition of these routines will always be available. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Mike Turquette <mturquette@linaro.org>
-
Saravana Kannan authored
Without this patch, the following race condition is possible. * clk-A has two parents - clk-X and clk-Y. * All three are disabled and clk-X is current parent. * Thread A: clk_set_parent(clk-A, clk-Y). * Thread A: <snip execution flow> * Thread A: Grabs enable lock. * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y. * Thread A: Updates clk-A SW parent to clk-Y * Thread A: Releases enable lock. * Thread B: clk_enable(clk-A). * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns. clk-A is now enabled in software, but not clocking in hardware since the hardware parent is still clk-X. The only way to avoid race conditions between clk_set_parent() and clk_enable/disable() is to ensure that clk_enable/disable() calls don't require changes to hardware enable state between changes to software clock topology and hardware clock topology. The options to achieve the above are: 1. Grab the enable lock before changing software/hardware topology and release it afterwards. 2. Keep the clock enabled for the duration of software/hardware topology change so that any additional enable/disable calls don't try to change the hardware state. Once the topology change is complete, the clock can be put back in its original enable state. Option (1) is not an acceptable solution since the set_parent() ops might need to sleep. Therefore, this patch implements option (2). This patch doesn't violate any API semantics. clk_disable() doesn't guarantee that the clock is actually disabled. So, no clients of a clock can assume that a clock is disabled after their last call to clk_disable(). So, enabling the clock during a parent change is not a violation of any API semantics. This also has the nice side effect of simplifying the error handling code. Signed-off-by:
Saravana Kannan <skannan@codeaurora.org> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up whitespace issue]
-