Commit 83907bf3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner'... 

Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next

* clk-bindings:
  dt-bindings: clock: ti,cdce925: Convert to DT schema

* clk-renesas: (26 commits)
  clk: renesas: r8a779f0: Fix Ethernet Switch clocks
  clk: renesas: r8a779g0: Add Z0 clock support
  clk: renesas: r8a779g0: Add CMT clocks
  clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
  clk: renesas: r8a779f0: Fix SCIF parent clocks
  clk: renesas: r8a779f0: Fix HSCIF parent clocks
  clk: renesas: r9a06g032: Repair grave increment error
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
  clk: renesas: r8a779a0: Fix SD0H clock name
  clk: renesas: r8a779g0: Add RPC-IF clock
  clk: renesas: r8a779g0: Add SDHI clocks
  clk: renesas: r8a779f0: Add SASYNCPER internal clock
  clk: renesas: r8a779f0: Fix SD0H clock name
  clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
  clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
  clk: renesas: r8a779g0: Add TPU clock
  clk: renesas: r8a779g0: Add PWM clock
  clk: renesas: r8a779g0: Add SCIF clocks
  clk: renesas: r9a07g044: Add MTU3a clock and reset entry
  ...

* clk-amlogic:
  clk: meson: pll: add pcie lock retry workaround
  clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()

* clk-allwinner:
  clk: sunxi-ng: f1c100s: Add IR mod clock
  clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.h

* clk-ti:
  clk: ti: fix typo in ti_clk_retry_init() code comment
  clk: ti: dra7-atl: don't allocate `parent_names' variable
  clk: ti: change ti_clk_register[_omap_hw]() API
parents a9fc882f 687daae7 01e6bf99 d0b1c692 9f8e3055 53949843

Documentation/devicetree/bindings/clock/ti,cdce925.txt

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Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.



Reference

This binding uses the common clock binding[1].



[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

[2] https://www.ti.com/product/cdce913

[3] https://www.ti.com/product/cdce925

[4] https://www.ti.com/product/cdce937

[5] https://www.ti.com/product/cdce949



The driver provides clock sources for each output Y1 through Y5.



Required properties:

 - compatible: Shall be one of the following:

	- "ti,cdce913": 1-PLL, 3 Outputs

	- "ti,cdce925": 2-PLL, 5 Outputs

	- "ti,cdce937": 3-PLL, 7 Outputs

	- "ti,cdce949": 4-PLL, 9 Outputs

 - reg: I2C device address.

 - clocks: Points to a fixed parent clock that provides the input frequency.

 - #clock-cells: From common clock bindings: Shall be 1.



Optional properties:

 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a

                 board, or to compensate for external influences.

- vdd-supply: A regulator node for Vdd

- vddout-supply: A regulator node for Vddout



For all PLL1, PLL2, ... an optional child node can be used to specify spread

spectrum clocking parameters for a board.

  - spread-spectrum: SSC mode as defined in the data sheet.

  - spread-spectrum-center: Use "centered" mode instead of "max" mode. When

    present, the clock runs at the requested frequency on average. Otherwise

    the requested frequency is the maximum value of the SCC range.





Example:



	clockgen: cdce925pw@64 {

		compatible = "cdce925";

		reg = <0x64>;

		clocks = <&xtal_27Mhz>;

		#clock-cells = <1>;

		xtal-load-pf = <5>;

		vdd-supply = <&1v8-reg>;

		vddout-supply = <&3v3-reg>;

		/* PLL options to get SSC 1% centered */

		PLL2 {

			spread-spectrum = <4>;

			spread-spectrum-center;

		};

	};

Documentation/devicetree/bindings/clock/ti,cdce925.yaml

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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: TI CDCE913/925/937/949 programmable I2C clock synthesizers



maintainers:

  - Alexander Stein <alexander.stein@ew.tq-group.com>



description: |

  Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction



  - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913

  - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925

  - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937

  - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949



properties:

  compatible:

    enum:

      - ti,cdce913

      - ti,cdce925

      - ti,cdce937

      - ti,cdce949



  reg:

    maxItems: 1



  clocks:

    items:

      - description: fixed parent clock



  "#clock-cells":

    const: 1



  vdd-supply:

    description: Regulator that provides 1.8V Vdd power supply



  vddout-supply:

    description: |

      Regulator that provides Vddout power supply.

      non-L variant: 2.5V or 3.3V for

      L variant: 1.8V for



  xtal-load-pf:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Crystal load-capacitor value to fine-tune performance on a

      board, or to compensate for external influences.



patternProperties:

  "^PLL[1-4]$":

    type: object

    description: |

      optional child node can be used to specify spread

      spectrum clocking parameters for a board



    additionalProperties: false



    properties:

      spread-spectrum:

        $ref: /schemas/types.yaml#/definitions/uint32

        description: SSC mode as defined in the data sheet



      spread-spectrum-center:

        type: boolean

        description: |

          Use "centered" mode instead of "max" mode. When

          present, the clock runs at the requested frequency on average.

          Otherwise the requested frequency is the maximum value of the

          SCC range.



required:

  - compatible

  - reg

  - clocks

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    i2c {

        #address-cells = <1>;

        #size-cells = <0>;



        cdce925: clock-controller@64 {

            compatible = "ti,cdce925";

            reg = <0x64>;

            clocks = <&xtal_27Mhz>;

            #clock-cells = <1>;

            xtal-load-pf = <5>;

            vdd-supply = <&reg_1v8>;

            vddout-supply = <&reg_3v3>;

            /* PLL options to get SSC 1% centered */

            PLL2 {

                spread-spectrum = <4>;

                spread-spectrum-center;

            };

        };

    };

drivers/clk/meson/clk-pll.c

+12 −8
Original line number Diff line number Diff line
@@ -276,15 +276,15 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) 
{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);

	int delay = 24000000;

	int delay = 5000;



	do {

		/* Is the clock locked now ? */

		/* Is the clock locked now ? Time out after 100ms. */

		if (meson_parm_read(clk->map, &pll->l))

			return 0;



		delay--;

	} while (delay > 0);

		udelay(20);

	} while (--delay);



	return -ETIMEDOUT;

}
@@ -319,12 +319,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) 


static int meson_clk_pcie_pll_enable(struct clk_hw *hw)

{

	int retries = 10;



	do {

		meson_clk_pll_init(hw);

		if (!meson_clk_pll_wait_lock(hw))

			return 0;

		pr_info("Retry enabling PCIe PLL clock\n");

	} while (--retries);



	if (meson_clk_pll_wait_lock(hw))

	return -EIO;



	return 0;

}



static int meson_clk_pll_enable(struct clk_hw *hw)

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),



	DEF_GEN4_SDH("sdh0",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SDH("sd0h",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),



	DEF_BASE("rpc",		R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+16 −12
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ enum clk_ids { 
	CLK_PLL5_DIV4,

	CLK_PLL6_DIV2,

	CLK_S0,

	CLK_SASYNCPER,

	CLK_SDSRC,

	CLK_RPCSRC,

	CLK_OCO,
@@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),

	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),



	DEF_FIXED(".sasyncper",	CLK_SASYNCPER,	CLK_PLL5_DIV4,	3, 1),

	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),

	DEF_RATE(".oco",	CLK_OCO,	32768),
@@ -109,11 +111,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_FIXED("sasyncrt",	R8A779F0_CLK_SASYNCRT,	CLK_PLL5_DIV4,	48, 1),

	DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),

	DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),

	DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),

	DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),

	DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),

	DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),



	DEF_GEN4_SDH("sdh0",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SDH("sd0h",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	R8A779F0_CLK_SD0H, 0x870),



	DEF_BASE("rpc",		R8A779F0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
@@ -126,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {

	DEF_MOD("hscif0",	514,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif1",	515,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif2",	516,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif3",	517,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif0",	514,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif3",	517,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("i2c0",		518,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779F0_CLK_S0D6_PER),
@@ -142,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("msiof3",	621,	R8A779F0_CLK_MSO),

	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),

	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),
@@ -161,6 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("cmt3",		913,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),

	DEF_MOD("rswitch2",	1505,	R8A779F0_CLK_RSW2),

	DEF_MOD("ether-serdes",	1506,	R8A779F0_CLK_S0D2_HSC),

	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),

};