Commit d0b1c692 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.2-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add 2 PLL driver fixups

* tag 'clk-meson-v6.2-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: pll: add pcie lock retry workaround
  clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()
parents 9abf2313 d73406ed

drivers/clk/meson/clk-pll.c

+12 −8
Original line number Diff line number Diff line
@@ -277,15 +277,15 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw) 
{

	struct clk_regmap *clk = to_clk_regmap(hw);

	struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);

	int delay = 24000000;

	int delay = 5000;



	do {

		/* Is the clock locked now ? */

		/* Is the clock locked now ? Time out after 100ms. */

		if (meson_parm_read(clk->map, &pll->l))

			return 0;



		delay--;

	} while (delay > 0);

		udelay(20);

	} while (--delay);



	return -ETIMEDOUT;

}
@@ -320,12 +320,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) 


static int meson_clk_pcie_pll_enable(struct clk_hw *hw)

{

	int retries = 10;



	do {

		meson_clk_pll_init(hw);

		if (!meson_clk_pll_wait_lock(hw))

			return 0;

		pr_info("Retry enabling PCIe PLL clock\n");

	} while (--retries);



	if (meson_clk_pll_wait_lock(hw))

	return -EIO;



	return 0;

}



static int meson_clk_pll_enable(struct clk_hw *hw)