Commit 01e6bf99 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.2-tag2' of... 

Merge tag 'renesas-clk-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Correct the parent clocks for the (High Speed) Serial Communication
   Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
   Switch clocks on R-Car S4-8
 - Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on R-Car
   V4H

* tag 'renesas-clk-for-v6.2-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779f0: Fix Ethernet Switch clocks
  clk: renesas: r8a779g0: Add Z0 clock support
  clk: renesas: r8a779g0: Add CMT clocks
  clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
  clk: renesas: r8a779f0: Fix SCIF parent clocks
  clk: renesas: r8a779f0: Fix HSCIF parent clocks
parents 57d894e7 777bcc85

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+10 −10
Original line number Diff line number Diff line
@@ -128,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {

	DEF_MOD("hscif0",	514,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif1",	515,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif2",	516,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif3",	517,	R8A779F0_CLK_S0D3),

	DEF_MOD("hscif0",	514,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("hscif3",	517,	R8A779F0_CLK_SASYNCPERD1),

	DEF_MOD("i2c0",		518,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779F0_CLK_S0D6_PER),
@@ -144,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("msiof3",	621,	R8A779F0_CLK_MSO),

	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),

	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_S0D12_PER),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif1",	703,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif3",	704,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("scif4",	705,	R8A779F0_CLK_SASYNCPERD4),

	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),
@@ -163,8 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("cmt3",		913,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsn",		1505,	R8A779F0_CLK_S0D2_HSC),

	DEF_MOD("rsw",		1506,	R8A779F0_CLK_RSW2),

	DEF_MOD("rswitch2",	1505,	R8A779F0_CLK_RSW2),

	DEF_MOD("ether-serdes",	1506,	R8A779F0_CLK_S0D2_HSC),

	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),

};

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+11 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED(".vc",	CLK_VC,		CLK_PLL5_DIV2,	3, 1),



	/* Core Clock Outputs */

	DEF_GEN4_Z("z0",	R8A779G0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	2, 0),

	DEF_FIXED("s0d2",	R8A779G0_CLK_S0D2,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3",	R8A779G0_CLK_S0D3,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4",	R8A779G0_CLK_S0D4,	CLK_S0,		4, 1),
@@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("s0d4_hsc",	R8A779G0_CLK_S0D4_HSC,	CLK_S0_HSC,	4, 1),

	DEF_FIXED("cl16m_hsc",	R8A779G0_CLK_CL16M_HSC,	CLK_S0_HSC,	48, 1),

	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),

	DEF_FIXED("sasyncrt",	R8A779G0_CLK_SASYNCRT,	CLK_PLL5_DIV4,	48, 1),

	DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),

	DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),

	DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
@@ -185,8 +187,17 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("sdhi",		706,	R8A779G0_CLK_SD0),

	DEF_MOD("sydm0",	709,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("sydm1",	710,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("tmu0",		713,	R8A779G0_CLK_SASYNCRT),

	DEF_MOD("tmu1",		714,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tmu2",		715,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tmu3",		716,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tpu0",		718,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("wdt1:wdt0",	907,	R8A779G0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779G0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779G0_CLK_R),

	DEF_MOD("cmt2",		912,	R8A779G0_CLK_R),

	DEF_MOD("cmt3",		913,	R8A779G0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),