Commit 57d894e7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.2-tag1' of... 

Merge tag 'renesas-clk-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Round SD clock rate to improve parent clock selection
 - Add Ethernet Switch and internal SASYNCPER clocks on R-Car S4-8
 - Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
   serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI (RPC-IF)
   clocks on R-Car V4H
 - Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
   RZ/G2L
 - Fix endless loop on RZ/N1
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (22 commits)
  clk: renesas: r9a06g032: Repair grave increment error
  clk: renesas: rzg2l: Don't assume all CPG_MOD clocks support PM
  clk: renesas: rzg2l: Fix typo in struct rzg2l_cpg_priv kerneldoc
  clk: renesas: r8a779a0: Fix SD0H clock name
  clk: renesas: r8a779g0: Add RPC-IF clock
  clk: renesas: r8a779g0: Add SDHI clocks
  clk: renesas: r8a779f0: Add SASYNCPER internal clock
  clk: renesas: r8a779f0: Fix SD0H clock name
  clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
  clk: renesas: r9a07g044: Drop WDT2 clock and reset entry
  clk: renesas: r8a779g0: Add TPU clock
  clk: renesas: r8a779g0: Add PWM clock
  clk: renesas: r8a779g0: Add SCIF clocks
  clk: renesas: r8a779g0: Fix HSCIF parent clocks
  clk: renesas: r8a779g0: Add SASYNCPER clocks
  clk: renesas: r9a07g044: Add MTU3a clock and reset entry
  clk: renesas: r8a779g0: Add INTC-EX clock
  clk: renesas: r8a779g0: Add MSIOF clocks
  clk: renesas: r8a779g0: Add SYS-DMAC clocks
  clk: renesas: r8a779f0: Add Ethernet Switch clocks
  ...
parents 9abf2313 02693e11

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cl16mck",	R8A779A0_CLK_CL16MCK,	CLK_PLL1_DIV2,	64, 1),



	DEF_GEN4_SDH("sdh0",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SDH("sd0h",	R8A779A0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779A0_CLK_SD0,	R8A779A0_CLK_SD0H, 0x870),



	DEF_BASE("rpc",		R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+8 −4
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ enum clk_ids { 
	CLK_PLL5_DIV4,

	CLK_PLL6_DIV2,

	CLK_S0,

	CLK_SASYNCPER,

	CLK_SDSRC,

	CLK_RPCSRC,

	CLK_OCO,
@@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED(".pll6_div2",	CLK_PLL6_DIV2,	CLK_PLL6,	2, 1),

	DEF_FIXED(".s0",	CLK_S0,		CLK_PLL1_DIV2,	2, 1),



	DEF_FIXED(".sasyncper",	CLK_SASYNCPER,	CLK_PLL5_DIV4,	3, 1),

	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),

	DEF_RATE(".oco",	CLK_OCO,	32768),
@@ -109,11 +111,11 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_FIXED("sasyncrt",	R8A779F0_CLK_SASYNCRT,	CLK_PLL5_DIV4,	48, 1),

	DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),

	DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),

	DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),

	DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),

	DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),

	DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),



	DEF_GEN4_SDH("sdh0",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SDH("sd0h",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	R8A779F0_CLK_SD0H, 0x870),



	DEF_BASE("rpc",		R8A779F0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
@@ -161,6 +163,8 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("cmt3",		913,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsn",		1505,	R8A779F0_CLK_S0D2_HSC),

	DEF_MOD("rsw",		1506,	R8A779F0_CLK_RSW2),

	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),

};

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+29 −6
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ enum clk_ids { 
	CLK_S0_VIO,

	CLK_S0_VC,

	CLK_S0_HSC,

	CLK_SASYNCPER,

	CLK_SV_VIP,

	CLK_SV_IR,

	CLK_SDSRC,
@@ -84,6 +85,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED(".s0_vio",	CLK_S0_VIO,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".s0_vc",	CLK_S0_VC,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".s0_hsc",	CLK_S0_HSC,	CLK_PLL1_DIV2,	2, 1),

	DEF_FIXED(".sasyncper",	CLK_SASYNCPER,	CLK_PLL5_DIV4,	3, 1),

	DEF_FIXED(".sv_vip",	CLK_SV_VIP,	CLK_PLL1,	5, 1),

	DEF_FIXED(".sv_ir",	CLK_SV_IR,	CLK_PLL1,	5, 1),

	DEF_BASE(".sdsrc",	CLK_SDSRC,	CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
@@ -128,6 +130,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("s0d4_hsc",	R8A779G0_CLK_S0D4_HSC,	CLK_S0_HSC,	4, 1),

	DEF_FIXED("cl16m_hsc",	R8A779G0_CLK_CL16M_HSC,	CLK_S0_HSC,	48, 1),

	DEF_FIXED("s0d2_cc",	R8A779G0_CLK_S0D2_CC,	CLK_S0,		2, 1),

	DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),

	DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),

	DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),

	DEF_FIXED("svd1_ir",	R8A779G0_CLK_SVD1_IR,	CLK_SV_IR,	1, 1),

	DEF_FIXED("svd2_ir",	R8A779G0_CLK_SVD2_IR,	CLK_SV_IR,	2, 1),

	DEF_FIXED("svd1_vip",	R8A779G0_CLK_SVD1_VIP,	CLK_SV_VIP,	1, 1),
@@ -139,7 +144,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),

	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VC,		2, 1),



	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	CLK_SDSRC,	0x870),

	DEF_GEN4_SDH("sd0h",	R8A779G0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	R8A779G0_CLK_SD0H, 0x870),

	DEF_DIV6P1("mso",	R8A779G0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),



	DEF_BASE("rpc",		R8A779G0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
@@ -153,16 +159,33 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_S0D3_PER),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif3",	517,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("i2c0",		518,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c1",		519,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c2",		520,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c3",		521,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c4",		522,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c5",		523,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("irqc",		611,	R8A779G0_CLK_CL16M),

	DEF_MOD("msi0",		618,	R8A779G0_CLK_MSO),

	DEF_MOD("msi1",		619,	R8A779G0_CLK_MSO),

	DEF_MOD("msi2",		620,	R8A779G0_CLK_MSO),

	DEF_MOD("msi3",		621,	R8A779G0_CLK_MSO),

	DEF_MOD("msi4",		622,	R8A779G0_CLK_MSO),

	DEF_MOD("msi5",		623,	R8A779G0_CLK_MSO),

	DEF_MOD("pwm",		628,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("rpc-if",	629,	R8A779G0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("scif1",	703,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("scif3",	704,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("scif4",	705,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("sdhi",		706,	R8A779G0_CLK_SD0),

	DEF_MOD("sydm0",	709,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("sydm1",	710,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("tpu0",		718,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("wdt1:wdt0",	907,	R8A779G0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),

drivers/clk/renesas/r9a06g032-clocks.c

+1 −2
Original line number Diff line number Diff line
@@ -412,7 +412,7 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd, 
	int error;

	int index;



	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,

	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,

					   &clkspec)) {

		if (clkspec.np != pd->dev.of_node)

			continue;
@@ -425,7 +425,6 @@ static int r9a06g032_attach_dev(struct generic_pm_domain *pd, 
			if (error)

				return error;

		}

		i++;

	}



	return 0;

drivers/clk/renesas/r9a07g043-cpg.c

+0 −5
Original line number Diff line number Diff line
@@ -158,10 +158,6 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 
				0x548, 0),

	DEF_MOD("wdt0_clk",	R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,

				0x548, 1),

	DEF_MOD("wdt2_pclk",	R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,

				0x548, 4),

	DEF_MOD("wdt2_clk",	R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,

				0x548, 5),

	DEF_MOD("spi_clk2",	R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,

				0x550, 0),

	DEF_MOD("spi_clk",	R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
@@ -269,7 +265,6 @@ static struct rzg2l_reset r9a07g043_resets[] = { 
	DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),

	DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),

	DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),

	DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),

	DEF_RST(R9A07G043_SPI_RST, 0x850, 0),

	DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),

	DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),