perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

mainline inclusion
from mainline-v5.16-rc1
commit 4034fb20
category: feature
feature: SPR PMU uncore support
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5BECO



Intel-SIG: commit 4034fb20 perf/x86/intel/uncore: Fix Intel SPR
M3UPI event constraints
This commit is backported as a fix to SPR PMU uncore support.

-------------------------------------

SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51ea ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Aichun Shi <aichun.shi@intel.com>