Commit 2a8e51ea authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support 



M3 Intel UPI is the interface between the mesh and the Intel UPI link
layer. It is responsible for translating between the mesh protocol
packets and the flits that are used for transmitting data across the
Intel UPI interface.

The layout of the control registers for a M3UPI uncore unit is similar
to a UPI uncore unit.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com
parent da5a9156

arch/x86/events/intel/uncore_snbep.c

+6 −1
Original line number Diff line number Diff line
@@ -5703,6 +5703,11 @@ static struct intel_uncore_type spr_uncore_upi = { 
	.name			= "upi",

};



static struct intel_uncore_type spr_uncore_m3upi = {

	SPR_UNCORE_PCI_COMMON_FORMAT(),

	.name			= "m3upi",

};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12



static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5715,7 +5720,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { 
	&spr_uncore_imc,

	&spr_uncore_m2m,

	&spr_uncore_upi,

	NULL,

	&spr_uncore_m3upi,

	NULL,

	NULL,

};