Commit da5a9156 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add Sapphire Rapids server UPI support 



Sapphire Rapids uses a coherent interconnect for scaling to multiple
sockets known as Intel UPI. Intel UPI technology provides a cache
coherent socket to socket external communication interface between
processors.

The layout of the control registers for a UPI uncore unit is similar to
a M2M uncore unit.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-10-git-send-email-kan.liang@linux.intel.com
parent f57191ed

arch/x86/events/intel/uncore_snbep.c

+6 −1
Original line number Diff line number Diff line
@@ -5698,6 +5698,11 @@ static struct intel_uncore_type spr_uncore_m2m = { 
	.name			= "m2m",

};



static struct intel_uncore_type spr_uncore_upi = {

	SPR_UNCORE_PCI_COMMON_FORMAT(),

	.name			= "upi",

};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12



static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5709,7 +5714,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { 
	NULL,

	&spr_uncore_imc,

	&spr_uncore_m2m,

	NULL,

	&spr_uncore_upi,

	NULL,

	NULL,

	NULL,