Commit f57191ed authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add Sapphire Rapids server M2M support 



The M2M blocks manage the interface between the mesh (operating on both
the mesh and the SMI3 protocol) and the memory controllers.

The layout of the control registers for a M2M uncore unit is a little
 bit different from the generic one. So a specific format and ops are
required. Expose the common PCI ops which can be reused.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-9-git-send-email-kan.liang@linux.intel.com
parent 85f2e30f

arch/x86/events/intel/uncore_discovery.c

+7 −7
Original line number Diff line number Diff line
@@ -377,7 +377,7 @@ static struct intel_uncore_ops generic_uncore_msr_ops = { 
	.read_counter		= uncore_msr_read_counter,

};



static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)

void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box)

{

	struct pci_dev *pdev = box->pci_dev;

	int box_ctl = uncore_pci_box_ctl(box);
@@ -386,7 +386,7 @@ static void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) 
	pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_INT);

}



static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)

void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box)

{

	struct pci_dev *pdev = box->pci_dev;

	int box_ctl = uncore_pci_box_ctl(box);
@@ -394,7 +394,7 @@ static void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box) 
	pci_write_config_dword(pdev, box_ctl, GENERIC_PMON_BOX_CTL_FRZ);

}



static void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)

void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box)

{

	struct pci_dev *pdev = box->pci_dev;

	int box_ctl = uncore_pci_box_ctl(box);
@@ -411,7 +411,7 @@ static void intel_generic_uncore_pci_enable_event(struct intel_uncore_box *box, 
	pci_write_config_dword(pdev, hwc->config_base, hwc->config);

}



static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,

void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,

					    struct perf_event *event)

{

	struct pci_dev *pdev = box->pci_dev;
@@ -420,7 +420,7 @@ static void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box, 
	pci_write_config_dword(pdev, hwc->config_base, 0);

}



static u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,

u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,

					  struct perf_event *event)

{

	struct pci_dev *pdev = box->pci_dev;

arch/x86/events/intel/uncore_discovery.h

+8 −0
Original line number Diff line number Diff line
@@ -140,5 +140,13 @@ void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box); 
void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,

					     struct perf_event *event);



void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);

void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);

void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);

void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,

					    struct perf_event *event);

u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,

					  struct perf_event *event);



struct intel_uncore_type **

intel_uncore_generic_init_uncores(enum uncore_access_type type_id);

arch/x86/events/intel/uncore_snbep.c

+29 −1
Original line number Diff line number Diff line
@@ -5670,6 +5670,34 @@ static struct intel_uncore_type spr_uncore_imc = { 
	.ops			= &spr_uncore_mmio_ops,

};



static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,

					struct perf_event *event)

{

	struct pci_dev *pdev = box->pci_dev;

	struct hw_perf_event *hwc = &event->hw;



	pci_write_config_dword(pdev, hwc->config_base + 4, (u32)(hwc->config >> 32));

	pci_write_config_dword(pdev, hwc->config_base, (u32)hwc->config);

}



static struct intel_uncore_ops spr_uncore_pci_ops = {

	.init_box		= intel_generic_uncore_pci_init_box,

	.disable_box		= intel_generic_uncore_pci_disable_box,

	.enable_box		= intel_generic_uncore_pci_enable_box,

	.disable_event		= intel_generic_uncore_pci_disable_event,

	.enable_event		= spr_uncore_pci_enable_event,

	.read_counter		= intel_generic_uncore_pci_read_counter,

};



#define SPR_UNCORE_PCI_COMMON_FORMAT()			\

	SPR_UNCORE_COMMON_FORMAT(),			\

	.ops			= &spr_uncore_pci_ops



static struct intel_uncore_type spr_uncore_m2m = {

	SPR_UNCORE_PCI_COMMON_FORMAT(),

	.name			= "m2m",

};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12



static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5680,7 +5708,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = { 
	&spr_uncore_pcu,

	NULL,

	&spr_uncore_imc,

	NULL,

	&spr_uncore_m2m,

	NULL,

	NULL,

	NULL,