Commit 4034fb20 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints 



SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51ea ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
parent f01d7d55

arch/x86/events/intel/uncore_snbep.c

+1 −0
Original line number Diff line number Diff line
@@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = { 
static struct intel_uncore_type spr_uncore_m3upi = {

	SPR_UNCORE_PCI_COMMON_FORMAT(),

	.name			= "m3upi",

	.constraints		= icx_uncore_m3upi_constraints,

};



static struct intel_uncore_type spr_uncore_mdf = {