Commit 7c15fd86 authored by Mauro Rossi's avatar Mauro Rossi Committed by Alex Deucher
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drm/amd/display: dc/dce: add initial DCE6 support (v10) 



[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this

[How]
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits

(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
     updated dce60 due to following kernel 5.0 commits:
     24f7dd7e ("drm/amd/display: move pplib/smu notification to dccg block")
     9566b675 ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
     4244381c ("drm/amd/display: clean up base dccg struct")
     4c5e8b54 ("drm/amd/display: split dccg clock manager into asic folders")
     84e7fc05 ("drm/amd/display: rename dccg to clk_mgr")
     77f6916a ("drm/amd/display: Remove duplicate header")
     9f7ddbea ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
     4ece61a2 ("drm/amd/display: set clocks to 0 on suspend on dce80")

(v3b) updated dce60 due to following kernel 5.1 commits:
     380604e2 ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
     32e61361 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
     1877ccf6 ("drm/amd/display: Change from aux_engine to dce_aux")
     c69dffab ("drm/amd/display: fix eDP fast bootup for pre-raven asic")

(v4b) updated dce60 due to following kernel 5.2 commits:
     e5c41970 ("drm/amd/display: Add plane capabilities to dc_caps")
     813d20dc ("drm/amd/display: Fix multi-thread writing to 1 state")
     ea36ad34 ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
     afcd526b ("drm/amd/display: Add fast_validate parameter")

(v5b) updated dce60 due to following kernel 5.3 commits:
     e7e10c46 ("drm/amd/display: stop external access to internal optc sync params")
     78cc70b1 ("drm/amd/display: Engine-specific encoder allocation")
     dc88b4a6 ("drm/amd/display: make clk mgr soc specific")
     4fc4dca8 ("drm/amd: drop use of drmp.h in os_types.h")

(v6b) updated dce60 due to following kernel 5.4 commits:
     54a9bcb0 ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
     9adc8050 ("drm/amd/display: make firmware info only load once during dc_bios create")

(v7b) updated dce60 due to following kernel 5.5 commits:
     cabe144b ("drm/amd/display: memory leak")
     8276dd87 ("drm/amd/display: update register field access mechanism")
     f6040a43 ("drm/amd/display: configurable aux timeout support")
     bf7f5ac3 ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")

(v8b) updated dce60 due to following kernel 5.6 commits:
     d9e32672 ("drm/amd/display: cleanup of construct and destruct funcs")
     f42ea55b ("drm/amd/display: add separate of private hwss functions")

(v9b) updated dce60 due to following kernel 5.8 commits:
     bba8289b ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
     904fb6e0 ("drm/amd/display: move panel power seq to new panel struct")
     d4caa72e ("drm/amd/display: change from panel to panel cntl")

(v10) Fix up PLL handling for DCE6:
     DCE6.0 supports 2 PLLs.  DCE6.1 supports 3 PLLs. (Alex)

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMauro Rossi <issor.oruam@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f233c098

drivers/gpu/drm/amd/display/dc/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,10 @@ DC_LIBS += dce110 
DC_LIBS += dce100

DC_LIBS += dce80



ifdef CONFIG_DRM_AMD_DC_SI

DC_LIBS += dce60

endif



ifdef CONFIG_DRM_AMD_DC_HDCP

DC_LIBS += hdcp

endif

drivers/gpu/drm/amd/display/dc/dce60/Makefile

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+34 −0
Original line number Diff line number Diff line 
#

# Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>

#

# Permission is hereby granted, free of charge, to any person obtaining a

# copy of this software and associated documentation files (the "Software"),

# to deal in the Software without restriction, including without limitation

# the rights to use, copy, modify, merge, publish, distribute, sublicense,

# and/or sell copies of the Software, and to permit persons to whom the

# Software is furnished to do so, subject to the following conditions:

#

# The above copyright notice and this permission notice shall be included in

# all copies or substantial portions of the Software.

#

# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

# OTHER DEALINGS IN THE SOFTWARE.

#

#

# Makefile for the 'controller' sub-component of DAL.

# It provides the control and status of HW CRTC block.



DCE60 = dce60_timing_generator.o dce60_hw_sequencer.o \

	dce60_resource.o



AMD_DAL_DCE60 = $(addprefix $(AMDDALPATH)/dc/dce60/,$(DCE60))



AMD_DISPLAY_FILES += $(AMD_DAL_DCE60)

drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.c

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+54 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "dm_services.h"

#include "dc.h"

#include "core_types.h"

#include "dce60_hw_sequencer.h"



#include "dce/dce_hwseq.h"

#include "dce110/dce110_hw_sequencer.h"

#include "dce100/dce100_hw_sequencer.h"



/* include DCE8 register header files */

#include "dce/dce_6_0_d.h"

#include "dce/dce_6_0_sh_mask.h"



/*******************************************************************************

 * Private definitions

 ******************************************************************************/



/***************************PIPE_CONTROL***********************************/



void dce60_hw_sequencer_construct(struct dc *dc)

{

	dce110_hw_sequencer_construct(dc);



	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;

	dc->hwss.pipe_control_lock = dce_pipe_control_lock;

	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;

	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;

}

drivers/gpu/drm/amd/display/dc/dce60/dce60_hw_sequencer.h

0 → 100644
+37 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DC_HWSS_DCE60_H__

#define __DC_HWSS_DCE60_H__



#include "core_types.h"

#include "hw_sequencer_private.h"



struct dc;



void dce60_hw_sequencer_construct(struct dc *dc);



#endif /* __DC_HWSS_DCE60_H__ */

drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c

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+1532 −0

File added.

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