Commit 904fb6e0 authored by Anthony Koo's avatar Anthony Koo Committed by Alex Deucher
Browse files

drm/amd/display: move panel power seq to new panel struct 



[Why]
panel power sequencer is currently just sitting in hwseq but it really
it tied to internal panels

[How]
make a new panel struct to contain power sequencer code

Signed-off-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fefe92fe

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+22 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ 
#include "hw/clk_mgr.h"

#include "dce/dmub_psr.h"

#include "dmub/inc/dmub_cmd_dal.h"

#include "inc/hw/panel.h"



#define DC_LOGGER_INIT(logger)
@@ -1355,6 +1356,7 @@ static bool dc_link_construct(struct dc_link *link, 
	struct ddc_service_init_data ddc_service_init_data = { { 0 } };

	struct dc_context *dc_ctx = init_params->ctx;

	struct encoder_init_data enc_init_data = { 0 };

	struct panel_init_data panel_init_data = { 0 };

	struct integrated_info info = {{{ 0 }}};

	struct dc_bios *bios = init_params->dc->ctx->dc_bios;

	const struct dc_vbios_funcs *bp_funcs = bios->funcs;
@@ -1425,6 +1427,7 @@ static bool dc_link_construct(struct dc_link *link, 
			link->irq_source_hpd_rx =

					dal_irq_get_rx_source(link->hpd_gpio);

		}



		break;

	case CONNECTOR_ID_LVDS:

		link->connector_signal = SIGNAL_TYPE_LVDS;
@@ -1454,6 +1457,22 @@ static bool dc_link_construct(struct dc_link *link, 
	link->ddc_hw_inst =

		dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));





	if (link->dc->res_pool->funcs->panel_create &&

		(link->link_id.id == CONNECTOR_ID_EDP ||

			link->link_id.id == CONNECTOR_ID_LVDS)) {

		panel_init_data.ctx = dc_ctx;

		panel_init_data.inst = 0;

		link->panel =

			link->dc->res_pool->funcs->panel_create(

								&panel_init_data);



		if (link->panel == NULL) {

			DC_ERROR("Failed to create link panel!\n");

			goto panel_create_fail;

		}

	}



	enc_init_data.ctx = dc_ctx;

	bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,

			      &enc_init_data.encoder);
@@ -1536,6 +1555,9 @@ static bool dc_link_construct(struct dc_link *link, 
device_tag_fail:

	link->link_enc->funcs->destroy(&link->link_enc);

link_enc_create_fail:

	if (link->panel != NULL)

		link->panel->funcs->destroy(&link->panel);

panel_create_fail:

	dal_ddc_service_destroy(&link->ddc);

ddc_create_fail:

create_fail:

drivers/gpu/drm/amd/display/dc/dc_link.h

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ struct dc_link { 


	struct dc_context *ctx;



	struct panel *panel;

	struct link_encoder *link_enc;

	struct graphics_object_id link_id;

	union ddi_channel_mapping ddi_channel_mapping;

drivers/gpu/drm/amd/display/dc/dce/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o dce_hwseq.o \

dce_mem_input.o dce_clock_source.o dce_scl_filters.o dce_transform.o \

dce_opp.o dce_dmcu.o dce_abm.o dce_ipp.o dce_aux.o \

dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o

dce_i2c.o dce_i2c_hw.o dce_i2c_sw.o dmub_psr.o dmub_abm.o dce_panel.o



AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+15 −50
Original line number Diff line number Diff line
@@ -27,10 +27,6 @@ 


#include "dc_types.h"



#define BL_REG_LIST()\

	SR(LVTMA_PWRSEQ_CNTL), \

	SR(LVTMA_PWRSEQ_STATE)



#define HWSEQ_DCEF_REG_LIST_DCE8() \

	.DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \

	.DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \
@@ -94,20 +90,17 @@ 
	SRII(BLND_CONTROL, BLND, 0),\

	SRII(BLND_CONTROL, BLND, 1),\

	SR(BLNDV_CONTROL),\

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\

	BL_REG_LIST()

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)



#define HWSEQ_DCE8_REG_LIST() \

	HWSEQ_DCEF_REG_LIST_DCE8(), \

	HWSEQ_BLND_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\

	BL_REG_LIST()

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)



#define HWSEQ_DCE10_REG_LIST() \

	HWSEQ_DCEF_REG_LIST(), \

	HWSEQ_BLND_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \

	BL_REG_LIST()

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)



#define HWSEQ_ST_REG_LIST() \

	HWSEQ_DCE11_REG_LIST_BASE(), \
@@ -134,8 +127,7 @@ 
	SR(DCHUB_FB_LOCATION),\

	SR(DCHUB_AGP_BASE),\

	SR(DCHUB_AGP_BOT),\

	SR(DCHUB_AGP_TOP), \

	BL_REG_LIST()

	SR(DCHUB_AGP_TOP)



#define HWSEQ_VG20_REG_LIST() \

	HWSEQ_DCE120_REG_LIST(),\
@@ -144,8 +136,7 @@ 
#define HWSEQ_DCE112_REG_LIST() \

	HWSEQ_DCE10_REG_LIST(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \

	HWSEQ_PHYPLL_REG_LIST(CRTC), \

	BL_REG_LIST()

	HWSEQ_PHYPLL_REG_LIST(CRTC)



#define HWSEQ_DCN_REG_LIST()\

	SR(REFCLK_CNTL), \
@@ -207,8 +198,7 @@ 
	SR(D3VGA_CONTROL), \

	SR(D4VGA_CONTROL), \

	SR(VGA_TEST_CONTROL), \

	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()

	SR(DC_IP_REQUEST_CNTL)



#define HWSEQ_DCN2_REG_LIST()\

	HWSEQ_DCN_REG_LIST(), \
@@ -273,8 +263,7 @@ 
	SR(D4VGA_CONTROL), \

	SR(D5VGA_CONTROL), \

	SR(D6VGA_CONTROL), \

	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()

	SR(DC_IP_REQUEST_CNTL)



#define HWSEQ_DCN21_REG_LIST()\

	HWSEQ_DCN_REG_LIST(), \
@@ -324,15 +313,9 @@ 
	SR(D4VGA_CONTROL), \

	SR(D5VGA_CONTROL), \

	SR(D6VGA_CONTROL), \

	SR(DC_IP_REQUEST_CNTL), \

	BL_REG_LIST()

	SR(DC_IP_REQUEST_CNTL)



struct dce_hwseq_registers {



		/* Backlight registers */

	uint32_t LVTMA_PWRSEQ_CNTL;

	uint32_t LVTMA_PWRSEQ_STATE;



	uint32_t DCFE_CLOCK_CONTROL[6];

	uint32_t DCFEV_CLOCK_CONTROL;

	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL;
@@ -465,26 +448,18 @@ struct dce_hwseq_registers { 
	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\

	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)



#define HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)\

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)



#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\

	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \

	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\

	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\

	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\

	HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)



#define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\

	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)



#define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\
@@ -507,8 +482,7 @@ struct dce_hwseq_registers { 
	HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\

	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh),\

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)

	HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)



#define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\
@@ -570,8 +544,7 @@ struct dce_hwseq_registers { 
	HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\

	HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\

	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\

	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)

	HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh)



#define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -630,8 +603,7 @@ struct dce_hwseq_registers { 
	HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)



#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\

	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -671,10 +643,7 @@ struct dce_hwseq_registers { 
	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \

	HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \

	HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)

	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh)



#define HWSEQ_REG_FIELD_LIST(type) \

	type DCFE_CLOCK_ENABLE; \
@@ -706,11 +675,7 @@ struct dce_hwseq_registers { 
	type PF_LFB_REGION;\

	type PF_MAX_REGION;\

	type ENABLE_L1_TLB;\

	type SYSTEM_ACCESS_MODE;\

	type LVTMA_BLON;\

	type LVTMA_DIGON;\

	type LVTMA_DIGON_OVRD;\

	type LVTMA_PWRSEQ_TARGET_STATE_R;

	type SYSTEM_ACCESS_MODE;



#define HWSEQ_DCN_REG_FIELD_LIST(type) \

	type HUBP_VTG_SEL; \

drivers/gpu/drm/amd/display/dc/dce/dce_panel.c

0 → 100644
+105 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2012-15 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#include "reg_helper.h"

#include "core_types.h"

#include "dc_dmub_srv.h"

#include "panel.h"

#include "dce_panel.h"



#define TO_DCE_PANEL(panel)\

	container_of(panel, struct dce_panel, base)



#define CTX \

	dce_panel->base.ctx



#define DC_LOGGER \

	dce_panel->base.ctx->logger



#define REG(reg)\

	dce_panel->regs->reg



#undef FN

#define FN(reg_name, field_name) \

	dce_panel->shift->field_name, dce_panel->mask->field_name



void dce_panel_hw_init(struct panel *panel)

{



}



bool dce_is_panel_backlight_on(struct panel *panel)

{

	struct dce_panel *dce_panel = TO_DCE_PANEL(panel);

	uint32_t value;



	REG_GET(PWRSEQ_CNTL, BLON, &value);



	return value;

}



bool dce_is_panel_powered_on(struct panel *panel)

{

	struct dce_panel *dce_panel = TO_DCE_PANEL(panel);

	uint32_t pwr_seq_state, dig_on, dig_on_ovrd;



	REG_GET(PWRSEQ_STATE, PWRSEQ_TARGET_STATE_R, &pwr_seq_state);



	REG_GET_2(PWRSEQ_CNTL, DIGON, &dig_on, DIGON_OVRD, &dig_on_ovrd);



	return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);

}



static void dce_panel_destroy(struct panel **panel)

{

	struct dce_panel *dce_panel = TO_DCE_PANEL(*panel);



	kfree(dce_panel);

	*panel = NULL;

}



static const struct panel_funcs dce_link_panel_funcs = {

	.destroy = dce_panel_destroy,

	.hw_init = dce_panel_hw_init,

	.is_panel_backlight_on = dce_is_panel_backlight_on,

	.is_panel_powered_on = dce_is_panel_powered_on,



};



void dce_panel_construct(

	struct dce_panel *dce_panel,

	const struct panel_init_data *init_data,

	const struct dce_panel_registers *regs,

	const struct dce_panel_shift *shift,

	const struct dce_panel_mask *mask)

{

	dce_panel->regs = regs;

	dce_panel->shift = shift;

	dce_panel->mask = mask;



	dce_panel->base.funcs = &dce_link_panel_funcs;

	dce_panel->base.ctx = init_data->ctx;

	dce_panel->base.inst = init_data->inst;

}