Commit 8276dd87 authored by abdoulaye berthe's avatar abdoulaye berthe Committed by Alex Deucher
Browse files

drm/amd/display: update register field access mechanism 



1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family

Signed-off-by: default avatarabdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarRoman Li <Roman.Li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 64c5cc93

drivers/gpu/drm/amd/display/dc/dce/dce_aux.c

+10 −1
Original line number Diff line number Diff line
@@ -42,6 +42,10 @@ 


#include "reg_helper.h"



#undef FN

#define FN(reg_name, field_name) \

	aux110->shift->field_name, aux110->mask->field_name



#define FROM_AUX_ENGINE(ptr) \

	container_of((ptr), struct aux_engine_dce110, base)
@@ -414,11 +418,14 @@ void dce110_engine_destroy(struct dce_aux **engine) 
	*engine = NULL;



}



struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,

		struct dc_context *ctx,

		uint32_t inst,

		uint32_t timeout_period,

		const struct dce110_aux_registers *regs)

		const struct dce110_aux_registers *regs,

		const struct dce110_aux_registers_mask *mask,

		const struct dce110_aux_registers_shift *shift)

{

	aux_engine110->base.ddc = NULL;

	aux_engine110->base.ctx = ctx;
@@ -428,6 +435,8 @@ struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine 
	aux_engine110->timeout_period = timeout_period;

	aux_engine110->regs = regs;



	aux_engine110->mask = mask;

	aux_engine110->shift = shift;

	return &aux_engine110->base;

}

drivers/gpu/drm/amd/display/dc/dce/dce_aux.h

+172 −3
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include "i2caux_interface.h"

#include "inc/hw/aux_engine.h"





#ifdef CONFIG_DRM_AMD_DC_DCN2_0

#define AUX_COMMON_REG_LIST0(id)\

	SRI(AUX_CONTROL, DP_AUX, id), \
@@ -36,6 +37,7 @@ 
	SRI(AUX_SW_DATA, DP_AUX, id), \

	SRI(AUX_SW_CONTROL, DP_AUX, id), \

	SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \

	SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \

	SRI(AUX_SW_STATUS, DP_AUX, id)

#endif
@@ -55,6 +57,7 @@ struct dce110_aux_registers { 
	uint32_t AUX_SW_DATA;

	uint32_t AUX_SW_CONTROL;

	uint32_t AUX_INTERRUPT_CONTROL;

	uint32_t AUX_DPHY_RX_CONTROL1;

	uint32_t AUX_SW_STATUS;

	uint32_t AUXN_IMPCAL;

	uint32_t AUXP_IMPCAL;
@@ -62,6 +65,156 @@ struct dce110_aux_registers { 
	uint32_t AUX_RESET_MASK;

};



#define DCE_AUX_REG_FIELD_LIST(type)\

	type AUX_EN;\

	type AUX_RESET;\

	type AUX_RESET_DONE;\

	type AUX_REG_RW_CNTL_STATUS;\

	type AUX_SW_USE_AUX_REG_REQ;\

	type AUX_SW_DONE_USING_AUX_REG;\

	type AUX_SW_AUTOINCREMENT_DISABLE;\

	type AUX_SW_DATA_RW;\

	type AUX_SW_INDEX;\

	type AUX_SW_GO;\

	type AUX_SW_DATA;\

	type AUX_SW_REPLY_BYTE_COUNT;\

	type AUX_SW_DONE;\

	type AUX_SW_DONE_ACK;\

	type AUXN_IMPCAL_ENABLE;\

	type AUXP_IMPCAL_ENABLE;\

	type AUXN_IMPCAL_OVERRIDE_ENABLE;\

	type AUXP_IMPCAL_OVERRIDE_ENABLE;\

	type AUX_RX_TIMEOUT_LEN;\

	type AUX_RX_TIMEOUT_LEN_MUL;\

	type AUXN_CALOUT_ERROR_AK;\

	type AUXP_CALOUT_ERROR_AK;\

	type AUX_SW_START_DELAY;\

	type AUX_SW_WR_BYTES



#define DCE10_AUX_MASK_SH_LIST(mask_sh)\

	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)



#define DCE_AUX_MASK_SH_LIST(mask_sh)\

	AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\

	AUX_SF(AUX_CONTROL, AUX_RESET, mask_sh),\

	AUX_SF(AUX_CONTROL, AUX_RESET_DONE, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\

	AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\

	AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

	AUX_SF(AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

	AUX_SF(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

	AUX_SF(AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

	AUX_SF(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)



#define DCE12_AUX_MASK_SH_LIST(mask_sh)\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)



/* DCN10 MASK */

#define DCN10_AUX_MASK_SH_LIST(mask_sh)\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_CALOUT_ERROR_AK, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_ENABLE, mask_sh),\

	AUX_SF(AUXP_IMPCAL, AUXP_IMPCAL_OVERRIDE_ENABLE, mask_sh),\

	AUX_SF(AUXN_IMPCAL, AUXN_IMPCAL_OVERRIDE_ENABLE, mask_sh)



/* for all other DCN */

#define DCN_AUX_MASK_SH_LIST(mask_sh)\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_EN, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET, mask_sh),\

	AUX_SF(DP_AUX0_AUX_CONTROL, AUX_RESET_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\

	AUX_SF(DP_AUX0_AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_DATA, AUX_SW_DATA, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, mask_sh),\

	AUX_SF(DP_AUX0_AUX_SW_STATUS, AUX_SW_DONE, mask_sh),\

	AUX_SF(DP_AUX0_AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, mask_sh),\

	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\

	AUX_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh)



#define AUX_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix



enum {	/* This is the timeout as defined in DP 1.2a,

	 * 2.3.4 "Detailed uPacket TX AUX CH State Description".

	 */
@@ -97,17 +250,31 @@ struct dce_aux { 
	uint32_t max_defer_write_retry;



	bool acquire_reset;

	const struct dce_aux_funcs *funcs;

};



struct dce110_aux_registers_mask {

	DCE_AUX_REG_FIELD_LIST(uint32_t);

};



struct dce110_aux_registers_shift {

	DCE_AUX_REG_FIELD_LIST(uint8_t);

};





struct aux_engine_dce110 {

	struct dce_aux base;

	const struct dce110_aux_registers *regs;

	const struct dce110_aux_registers_mask *mask;

	const struct dce110_aux_registers_shift *shift;

	struct {

		uint32_t aux_control;

		uint32_t aux_arb_control;

		uint32_t aux_sw_data;

		uint32_t aux_sw_control;

		uint32_t aux_interrupt_control;

		uint32_t aux_dphy_rx_control1;

		uint32_t aux_dphy_rx_control0;

		uint32_t aux_sw_status;

	} addr;

	uint32_t timeout_period;
@@ -120,12 +287,14 @@ struct aux_engine_dce110_init_data { 
	const struct dce110_aux_registers *regs;

};



struct dce_aux *dce110_aux_engine_construct(

		struct aux_engine_dce110 *aux_engine110,

struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 *aux_engine110,

		struct dc_context *ctx,

		uint32_t inst,

		uint32_t timeout_period,

		const struct dce110_aux_registers *regs);

		const struct dce110_aux_registers *regs,



		const struct dce110_aux_registers_mask *mask,

		const struct dce110_aux_registers_shift *shift);



void dce110_engine_destroy(struct dce_aux **engine);

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+11 −1
Original line number Diff line number Diff line
@@ -506,6 +506,14 @@ static const struct dce_mem_input_mask mi_masks = { 
		.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

};



static const struct dce110_aux_registers_shift aux_shift = {

	DCE10_AUX_MASK_SH_LIST(__SHIFT)

};



static const struct dce110_aux_registers_mask aux_mask = {

	DCE10_AUX_MASK_SH_LIST(_MASK)

};



static struct mem_input *dce100_mem_input_create(

	struct dc_context *ctx,

	uint32_t inst)
@@ -611,7 +619,9 @@ struct dce_aux *dce100_aux_engine_create( 


	dce110_aux_engine_construct(aux_engine, ctx, inst,

				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

				    &aux_engine_regs[inst]);

				    &aux_engine_regs[inst],

					&aux_mask,

					&aux_shift);



	return &aux_engine->base;

}

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

+11 −1
Original line number Diff line number Diff line
@@ -275,6 +275,14 @@ static const struct dce_stream_encoder_mask se_mask = { 
		SE_COMMON_MASK_SH_LIST_DCE110(_MASK)

};



static const struct dce110_aux_registers_shift aux_shift = {

	DCE_AUX_MASK_SH_LIST(__SHIFT)

};



static const struct dce110_aux_registers_mask aux_mask = {

	DCE_AUX_MASK_SH_LIST(_MASK)

};



#define opp_regs(id)\

[id] = {\

	OPP_DCE_110_REG_LIST(id),\
@@ -657,7 +665,9 @@ struct dce_aux *dce110_aux_engine_create( 


	dce110_aux_engine_construct(aux_engine, ctx, inst,

				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

				    &aux_engine_regs[inst]);

				    &aux_engine_regs[inst],

					&aux_mask,

					&aux_shift);



	return &aux_engine->base;

}

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

+11 −1
Original line number Diff line number Diff line
@@ -172,6 +172,14 @@ static const struct dce_abm_mask abm_mask = { 
		ABM_MASK_SH_LIST_DCE110(_MASK)

};



static const struct dce110_aux_registers_shift aux_shift = {

	DCE_AUX_MASK_SH_LIST(__SHIFT)

};



static const struct dce110_aux_registers_mask aux_mask = {

	DCE_AUX_MASK_SH_LIST(_MASK)

};



#define ipp_regs(id)\

[id] = {\

		IPP_DCE110_REG_LIST_DCE_BASE(id)\
@@ -630,7 +638,9 @@ struct dce_aux *dce112_aux_engine_create( 


	dce110_aux_engine_construct(aux_engine, ctx, inst,

				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,

				    &aux_engine_regs[inst]);

				    &aux_engine_regs[inst],

					&aux_mask,

					&aux_shift);



	return &aux_engine->base;

}