Commit 6e7a9f0c authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas',... 

Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlogic' and 'clk-allwinner' into clk-next

 - Support dangerous debugfs actions on clks with dead code
 - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs

* clk-debugfs-danger:
  clk: Add support for setting clk_rate via debugfs

* clk-basic-hw:
  clk: divider: Add support for specifying parents via DT/pointers
  clk: gate: Add support for specifying parents via DT/pointers
  clk: mux: Add support for specifying parents via DT/pointers
  clk: asm9260: Use parent accuracy in fixed rate clk
  clk: fixed-rate: Document that accuracy isn't a rate
  clk: fixed-rate: Add clk flags for parent accuracy
  clk: fixed-rate: Add support for specifying parents via DT/pointers
  clk: fixed-rate: Document accuracy member
  clk: fixed-rate: Move to_clk_fixed_rate() to C file
  clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy()
  clk: fixed-rate: Convert to clk_hw based APIs
  clk: gpio: Use DT way of specifying parents

* clk-renesas:
  clk: renesas: Prepare for split of R-Car H3 config symbol
  dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
  clk: renesas: r7s9210: Add SPIBSC clock
  clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
  clk: renesas: Remove use of ARCH_R8A7796
  clk: renesas: rcar-gen2: Change multipliers and dividers to u8

* clk-amlogic:
  clk: clarify that clk_set_rate() does updates from top to bottom
  clk: meson: meson8b: make the CCF use the glitch-free mali mux
  clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
  clk: meson: g12a: fix missing uart2 in regmap table
  clk: meson: meson8b: use of_clk_hw_register to register the clocks
  clk: meson: meson8b: don't register the XTAL clock when provided via OF
  clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
  clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
  clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding

* clk-allwinner:
  clk: sunxi: a23/a33: Export the MIPI PLL
  clk: sunxi: a31: Export the MIPI PLL
  clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS
  clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
  clk: sunxi-ng: r40: Export MBUS clock
  clk: sunxi: use of_device_get_match_data
parents 36bf7a5b 37215da5 ff258817 c1c95a46 31ef0917 fa9ae305

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

0 → 100644
+50 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic DDR Clock Controller Device Tree Bindings



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



properties:

  compatible:

    enum:

      - amlogic,meson8-ddr-clkc

      - amlogic,meson8b-ddr-clkc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: xtal



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    ddr_clkc: clock-controller@400 {

      compatible = "amlogic,meson8-ddr-clkc";

      reg = <0x400 0x20>;

      clocks = <&xtal>;

      clock-names = "xtal";

      #clock-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

+5 −0
Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ Required Properties: 
	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- #clock-cells: should be 1.

- #reset-cells: should be 1.

- clocks: list of clock phandles, one for each entry in clock-names

- clock-names: should contain the following:

  * "xtal": the 24MHz system oscillator

  * "ddr_pll": the DDR PLL clock

  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)



Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ Required Properties: 
      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

drivers/clk/clk-asm9260.c

+4 −4
Original line number Diff line number Diff line
@@ -260,7 +260,6 @@ static void __init asm9260_acc_init(struct device_node *np) 
	const char *ref_clk, *pll_clk = "pll";

	u32 rate;

	int n;

	u32 accuracy = 0;



	clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);

	if (!clk_data)
@@ -275,10 +274,11 @@ static void __init asm9260_acc_init(struct device_node *np) 
	/* register pll */

	rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;



	/* TODO: Convert to DT parent scheme */

	ref_clk = of_clk_get_parent_name(np, 0);

	accuracy = clk_get_accuracy(__clk_lookup(ref_clk));

	hw = clk_hw_register_fixed_rate_with_accuracy(NULL, pll_clk,

			ref_clk, 0, rate, accuracy);

	hw = __clk_hw_register_fixed_rate_with_accuracy(NULL, NULL, pll_clk,

			ref_clk, NULL, NULL, 0, rate, 0,

			CLK_FIXED_RATE_PARENT_ACCURACY);



	if (IS_ERR(hw))

		panic("%pOFn: can't register REFCLK. Check DT!", np);

drivers/clk/clk-divider.c

+10 −81
Original line number Diff line number Diff line
@@ -463,11 +463,12 @@ const struct clk_ops clk_divider_ro_ops = { 
};

EXPORT_SYMBOL_GPL(clk_divider_ro_ops);



static struct clk_hw *_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

struct clk_hw *__clk_hw_register_divider(struct device *dev,

		struct device_node *np, const char *name,

		const char *parent_name, const struct clk_hw *parent_hw,

		const struct clk_parent_data *parent_data, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,

		const struct clk_div_table *table, spinlock_t *lock)

{

	struct clk_divider *div;

	struct clk_hw *hw;
@@ -514,55 +515,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name, 


	return hw;

}



/**

 * clk_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk *clk_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider);



/**

 * clk_hw_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider);

EXPORT_SYMBOL_GPL(__clk_hw_register_divider);



/**

 * clk_register_divider_table - register a table based divider clock with
@@ -586,39 +539,15 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, 
{

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

	hw =  __clk_hw_register_divider(dev, NULL, name, parent_name, NULL,

			NULL, flags, reg, shift, width, clk_divider_flags,

			table, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider_table);



/**

 * clk_hw_register_divider_table - register a table based divider clock with

 * the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider_table(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);



void clk_unregister_divider(struct clk *clk)

{

	struct clk_divider *div;