Commit 31ef0917 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add meson8b DDR clock controller
 - Add input clocks to meson8b controllers
 - Fix meson8b mali clock update using the glitch free mux
 - Fix pll driver division by zero init

* tag 'clk-meson-v5.6-1' of https://github.com/BayLibre/clk-meson:
  clk: clarify that clk_set_rate() does updates from top to bottom
  clk: meson: meson8b: make the CCF use the glitch-free mali mux
  clk: meson: pll: Fix by 0 division in __pll_params_to_rate()
  clk: meson: g12a: fix missing uart2 in regmap table
  clk: meson: meson8b: use of_clk_hw_register to register the clocks
  clk: meson: meson8b: don't register the XTAL clock when provided via OF
  clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
  clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
  clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
  dt-bindings: clock: meson8b: add the clock inputs
  dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
parents e42617b8 64c76b31

Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic DDR Clock Controller Device Tree Bindings



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



properties:

  compatible:

    enum:

      - amlogic,meson8-ddr-clkc

      - amlogic,meson8b-ddr-clkc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: xtal



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    ddr_clkc: clock-controller@400 {

      compatible = "amlogic,meson8-ddr-clkc";

      reg = <0x400 0x20>;

      clocks = <&xtal>;

      clock-names = "xtal";

      #clock-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

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@@ -11,6 +11,11 @@ Required Properties: 
	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- #clock-cells: should be 1.

- #reset-cells: should be 1.

- clocks: list of clock phandles, one for each entry in clock-names

- clock-names: should contain the following:

  * "xtal": the 24MHz system oscillator

  * "ddr_pll": the DDR PLL clock

  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)



Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

drivers/clk/meson/Makefile

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@@ -18,4 +18,4 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o 
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o

obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o

obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
 
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

drivers/clk/meson/clk-pll.c

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@@ -77,6 +77,15 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, 
	unsigned int m, n, frac;



	n = meson_parm_read(clk->map, &pll->n);



	/*

	 * On some HW, N is set to zero on init. This value is invalid as

	 * it would result in a division by zero. The rate can't be

	 * calculated in this case

	 */

	if (n == 0)

		return 0;



	m = meson_parm_read(clk->map, &pll->m);



	frac = MESON_PARM_APPLICABLE(&pll->frac) ?

drivers/clk/meson/g12a.c

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@@ -4692,6 +4692,7 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { 
	&g12a_bt656,

	&g12a_usb1_to_ddr,

	&g12a_mmc_pclk,

	&g12a_uart2,

	&g12a_vpu_intr,

	&g12a_gic,

	&g12a_sd_emmc_a_clk0,