Commit c1c95a46 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v5.6-tag1' of... 

Merge tag 'clk-renesas-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add SPIBSC (SPI FLASH) clock on RZ/A2
  - Prepare for split of R-Car H3 ES1.x and ES2.0+ config symbols

* tag 'clk-renesas-for-v5.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Prepare for split of R-Car H3 config symbol
  dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo
  clk: renesas: r7s9210: Add SPIBSC clock
  clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
  clk: renesas: Remove use of ARCH_R8A7796
  clk: renesas: rcar-gen2: Change multipliers and dividers to u8
parents e42617b8 8040bf40

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ Required Properties: 
      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)

      - "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)

      - "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

drivers/clk/renesas/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -20,8 +20,8 @@ config CLK_RENESAS 
	select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793

	select CLK_R8A7792 if ARCH_R8A7792

	select CLK_R8A7794 if ARCH_R8A7794

	select CLK_R8A7795 if ARCH_R8A7795

	select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796

	select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 || ARCH_R8A7795

	select CLK_R8A77960 if ARCH_R8A77960

	select CLK_R8A77961 if ARCH_R8A77961

	select CLK_R8A77965 if ARCH_R8A77965

	select CLK_R8A77970 if ARCH_R8A77970

drivers/clk/renesas/r7s9210-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = { 
	DEF_MOD_STB("ether1",	 64,	R7S9210_CLK_B),

	DEF_MOD_STB("ether0",	 65,	R7S9210_CLK_B),



	DEF_MOD_STB("spibsc",	 83,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c3",	 84,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c2",	 85,	R7S9210_CLK_P1),

	DEF_MOD_STB("i2c1",	 86,	R7S9210_CLK_P1),

drivers/clk/renesas/rcar-gen2-cpg.h

+4 −4
Original line number Diff line number Diff line
@@ -24,10 +24,10 @@ enum rcar_gen2_clk_types { 
};



struct rcar_gen2_cpg_pll_config {

	unsigned int extal_div;

	unsigned int pll1_mult;

	unsigned int pll3_mult;

	unsigned int pll0_mult;		/* leave as zero if PLL0CR exists */

	u8 extal_div;

	u8 pll1_mult;

	u8 pll3_mult;

	u8 pll0_mult;		/* leave as zero if PLL0CR exists */

};



struct clk *rcar_gen2_cpg_clk_register(struct device *dev,

drivers/clk/renesas/rcar-gen3-cpg.c

+4 −2
Original line number Diff line number Diff line
@@ -470,7 +470,8 @@ static struct clk * __init cpg_rpc_clk_register(const char *name, 


	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,

				     &rpc->div.hw,  &clk_divider_ops,

				     &rpc->gate.hw, &clk_gate_ops, 0);

				     &rpc->gate.hw, &clk_gate_ops,

				     CLK_SET_RATE_PARENT);

	if (IS_ERR(clk)) {

		kfree(rpc);

		return clk;
@@ -506,7 +507,8 @@ static struct clk * __init cpg_rpcd2_clk_register(const char *name, 


	clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,

				     &rpcd2->fixed.hw, &clk_fixed_factor_ops,

				     &rpcd2->gate.hw, &clk_gate_ops, 0);

				     &rpcd2->gate.hw, &clk_gate_ops,

				     CLK_SET_RATE_PARENT);

	if (IS_ERR(clk))

		kfree(rpcd2);