Commit ff258817 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

clk: divider: Add support for specifying parents via DT/pointers 



After commit fc0c209c ("clk: Allow parents to be specified without
string names") we can use DT or direct clk_hw pointers to specify
parents. Create a generic function that shouldn't be used very often to
encode the multitude of ways of registering a divider clk with different
parent information. Then add a bunch of wrapper macros that only pass
down what needs to be passed down to the generic function to support
this with less arguments.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190830150923.259497-13-sboyd@kernel.org
[sboyd@kernel.org: Export __clk_hw_register_divider]
parent 194efb6e

drivers/clk/clk-divider.c

+10 −81
Original line number Diff line number Diff line
@@ -463,11 +463,12 @@ const struct clk_ops clk_divider_ro_ops = { 
};

EXPORT_SYMBOL_GPL(clk_divider_ro_ops);



static struct clk_hw *_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

struct clk_hw *__clk_hw_register_divider(struct device *dev,

		struct device_node *np, const char *name,

		const char *parent_name, const struct clk_hw *parent_hw,

		const struct clk_parent_data *parent_data, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,

		const struct clk_div_table *table, spinlock_t *lock)

{

	struct clk_divider *div;

	struct clk_hw *hw;
@@ -514,55 +515,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name, 


	return hw;

}



/**

 * clk_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk *clk_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider);



/**

 * clk_hw_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, NULL, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider);

EXPORT_SYMBOL_GPL(__clk_hw_register_divider);



/**

 * clk_register_divider_table - register a table based divider clock with
@@ -586,39 +539,15 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, 
{

	struct clk_hw *hw;



	hw =  _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

	hw =  __clk_hw_register_divider(dev, NULL, name, parent_name, NULL,

			NULL, flags, reg, shift, width, clk_divider_flags,

			table, lock);

	if (IS_ERR(hw))

		return ERR_CAST(hw);

	return hw->clk;

}

EXPORT_SYMBOL_GPL(clk_register_divider_table);



/**

 * clk_hw_register_divider_table - register a table based divider clock with

 * the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

struct clk_hw *clk_hw_register_divider_table(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock)

{

	return _register_divider(dev, name, parent_name, flags, reg, shift,

			width, clk_divider_flags, table, lock);

}

EXPORT_SYMBOL_GPL(clk_hw_register_divider_table);



void clk_unregister_divider(struct clk *clk)

{

	struct clk_divider *div;

include/linux/clk-provider.h

+142 −13
Original line number Diff line number Diff line
@@ -626,24 +626,153 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate, 
		const struct clk_div_table *table, u8 width,

		unsigned long flags);



struct clk *clk_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock);

struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, spinlock_t *lock);

struct clk_hw *__clk_hw_register_divider(struct device *dev,

		struct device_node *np, const char *name,

		const char *parent_name, const struct clk_hw *parent_hw,

		const struct clk_parent_data *parent_data, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,

		const struct clk_div_table *table, spinlock_t *lock);

struct clk *clk_register_divider_table(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock);

struct clk_hw *clk_hw_register_divider_table(struct device *dev,

		const char *name, const char *parent_name, unsigned long flags,

		void __iomem *reg, u8 shift, u8 width,

		u8 clk_divider_flags, const struct clk_div_table *table,

		spinlock_t *lock);

/**

 * clk_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \

			     clk_divider_flags, lock)			       \

	clk_register_divider_table((dev), (name), (parent_name), (flags),      \

				   (reg), (shift), (width),		       \

				   (clk_divider_flags), NULL, (lock))

/**

 * clk_hw_register_divider - register a divider clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \

				width, clk_divider_flags, lock)		      \

	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \

				  NULL, (flags), (reg), (shift), (width),     \

				  (clk_divider_flags), NULL, (lock))

/**

 * clk_hw_register_divider_parent_hw - register a divider clock with the clock

 * framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_hw: pointer to parent clk

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \

					  shift, width, clk_divider_flags,    \

					  lock)				      \

	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \

				  NULL, (flags), (reg), (shift), (width),     \

				  (clk_divider_flags), NULL, (lock))

/**

 * clk_hw_register_divider_parent_data - register a divider clock with the clock

 * framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_data: parent clk data

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags,    \

					    reg, shift, width,		      \

					    clk_divider_flags, lock)	      \

	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \

				  (parent_data), (flags), (reg), (shift),     \

				  (width), (clk_divider_flags), NULL, (lock))

/**

 * clk_hw_register_divider_table - register a table based divider clock with

 * the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_name: name of clock's parent

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \

				      shift, width, clk_divider_flags, table, \

				      lock)				      \

	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \

				  NULL, (flags), (reg), (shift), (width),     \

				  (clk_divider_flags), (table), (lock))

/**

 * clk_hw_register_divider_table_parent_hw - register a table based divider

 * clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_hw: pointer to parent clk

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags,  \

						reg, shift, width,	      \

						clk_divider_flags, table,     \

						lock)			      \

	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \

				  NULL, (flags), (reg), (shift), (width),     \

				  (clk_divider_flags), (table), (lock))

/**

 * clk_hw_register_divider_table_parent_data - register a table based divider

 * clock with the clock framework

 * @dev: device registering this clock

 * @name: name of this clock

 * @parent_data: parent clk data

 * @flags: framework-specific flags

 * @reg: register address to adjust divider

 * @shift: number of bits to shift the bitfield

 * @width: width of the bitfield

 * @clk_divider_flags: divider-specific flags for this clock

 * @table: array of divider/value pairs ending with a div set to 0

 * @lock: shared register lock for this clock

 */

#define clk_hw_register_divider_table_parent_data(dev, name, parent_data,     \

						  flags, reg, shift, width,   \

						  clk_divider_flags, table,   \

						  lock)			      \

	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \

				  (parent_data), (flags), (reg), (shift),     \

				  (width), (clk_divider_flags), (table),      \

				  (lock))



void clk_unregister_divider(struct clk *clk);

void clk_hw_unregister_divider(struct clk_hw *hw);