perf/x86/uncore: Correct the number of CHAs on SPR

mainline inclusion
from mainline-v6.4-rc4
commit 38776cc4
category: bugfix
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8AR40
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38776cc45eb7603df4735a0410f42cffff8e71a1



Intel-SIG: commit 38776cc4 perf/x86/uncore: Correct the number of CHAs on SPR
Backport SPR and EMR PMU related upstream bugfixes to kernel 5.10.

-------------------------------------

The number of CHAs from the discovery table on some SPR variants is
incorrect, because of a firmware issue. An accurate number can be read
from the MSR UNC_CBO_CONFIG.

Fixes: 949b1138 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Stephane Eranian <eranian@google.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230508140206.283708-1-kan.liang@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>