Commit 949b1138 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Add Sapphire Rapids server CHA support 



CHA merges the caching agent and Home Agent (HA) responsibilities of the
chip into a single block. It's one of the Sapphire Rapids server uncore
units.

The layout of the control registers for a CHA uncore unit is a little
bit different from the generic one. The CHA uncore unit also supports a
filter register for TID. So a specific format and ops are required.
Expose the common MSR ops which can be reused.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-3-git-send-email-kan.liang@linux.intel.com
parent c54c53d9

arch/x86/events/intel/uncore_discovery.c

+3 −3
Original line number Diff line number Diff line
@@ -337,17 +337,17 @@ static const struct attribute_group generic_uncore_format_group = { 
	.attrs = generic_uncore_formats_attr,

};



static void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)

void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box)

{

	wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_INT);

}



static void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)

void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box)

{

	wrmsrl(uncore_msr_box_ctl(box), GENERIC_PMON_BOX_CTL_FRZ);

}



static void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)

void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box)

{

	wrmsrl(uncore_msr_box_ctl(box), 0);

}

arch/x86/events/intel/uncore_discovery.h

+4 −0
Original line number Diff line number Diff line
@@ -130,5 +130,9 @@ void intel_uncore_generic_uncore_cpu_init(void); 
int intel_uncore_generic_uncore_pci_init(void);

void intel_uncore_generic_uncore_mmio_init(void);



void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);

void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);

void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);



struct intel_uncore_type **

intel_uncore_generic_init_uncores(enum uncore_access_type type_id);

arch/x86/events/intel/uncore_snbep.c

+89 −1
Original line number Diff line number Diff line
@@ -455,6 +455,17 @@ 
#define ICX_NUMBER_IMC_CHN			2

#define ICX_IMC_MEM_STRIDE			0x4



/* SPR */

#define SPR_RAW_EVENT_MASK_EXT			0xffffff



/* SPR CHA */

#define SPR_CHA_PMON_CTL_TID_EN			(1 << 16)

#define SPR_CHA_PMON_EVENT_MASK			(SNBEP_PMON_RAW_EVENT_MASK | \

						 SPR_CHA_PMON_CTL_TID_EN)

#define SPR_CHA_PMON_BOX_FILTER_TID		0x3ff



#define SPR_C0_MSR_PMON_BOX_FILTER0		0x200e



DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");

DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");

DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
@@ -467,6 +478,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55"); 
DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");

DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");

DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");

DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16");

DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");

DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35");

DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
@@ -5508,10 +5520,86 @@ void icx_uncore_mmio_init(void) 


/* SPR uncore support */



static void spr_uncore_msr_enable_event(struct intel_uncore_box *box,

					struct perf_event *event)

{

	struct hw_perf_event *hwc = &event->hw;

	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;



	if (reg1->idx != EXTRA_REG_NONE)

		wrmsrl(reg1->reg, reg1->config);



	wrmsrl(hwc->config_base, hwc->config);

}



static void spr_uncore_msr_disable_event(struct intel_uncore_box *box,

					 struct perf_event *event)

{

	struct hw_perf_event *hwc = &event->hw;

	struct hw_perf_event_extra *reg1 = &hwc->extra_reg;



	if (reg1->idx != EXTRA_REG_NONE)

		wrmsrl(reg1->reg, 0);



	wrmsrl(hwc->config_base, 0);

}



static int spr_cha_hw_config(struct intel_uncore_box *box, struct perf_event *event)

{

	struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;

	bool tie_en = !!(event->hw.config & SPR_CHA_PMON_CTL_TID_EN);

	struct intel_uncore_type *type = box->pmu->type;



	if (tie_en) {

		reg1->reg = SPR_C0_MSR_PMON_BOX_FILTER0 +

			    HSWEP_CBO_MSR_OFFSET * type->box_ids[box->pmu->pmu_idx];

		reg1->config = event->attr.config1 & SPR_CHA_PMON_BOX_FILTER_TID;

		reg1->idx = 0;

	}



	return 0;

}



static struct intel_uncore_ops spr_uncore_chabox_ops = {

	.init_box		= intel_generic_uncore_msr_init_box,

	.disable_box		= intel_generic_uncore_msr_disable_box,

	.enable_box		= intel_generic_uncore_msr_enable_box,

	.disable_event		= spr_uncore_msr_disable_event,

	.enable_event		= spr_uncore_msr_enable_event,

	.read_counter		= uncore_msr_read_counter,

	.hw_config		= spr_cha_hw_config,

	.get_constraint		= uncore_get_constraint,

	.put_constraint		= uncore_put_constraint,

};



static struct attribute *spr_uncore_cha_formats_attr[] = {

	&format_attr_event.attr,

	&format_attr_umask_ext4.attr,

	&format_attr_tid_en2.attr,

	&format_attr_edge.attr,

	&format_attr_inv.attr,

	&format_attr_thresh8.attr,

	&format_attr_filter_tid5.attr,

	NULL,

};

static const struct attribute_group spr_uncore_chabox_format_group = {

	.name = "format",

	.attrs = spr_uncore_cha_formats_attr,

};



static struct intel_uncore_type spr_uncore_chabox = {

	.name			= "cha",

	.event_mask		= SPR_CHA_PMON_EVENT_MASK,

	.event_mask_ext		= SPR_RAW_EVENT_MASK_EXT,

	.num_shared_regs	= 1,

	.ops			= &spr_uncore_chabox_ops,

	.format_group		= &spr_uncore_chabox_format_group,

};



#define UNCORE_SPR_NUM_UNCORE_TYPES		12



static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {

	NULL,

	&spr_uncore_chabox,

	NULL,

	NULL,

	NULL,