Commit 0e2c9884 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mediatek', 'clk-trace', 'clk-qcom' and 'clk-microchip' into clk-next

 - Tracepoints for clk_rate_request structures

* clk-mediatek:
  clk: mediatek: fix dependency of MT7986 ADC clocks
  clk: mediatek: Change PLL register API for MT8186
  clk: mediatek: Add new clock driver to handle FHCTL hardware
  dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
  clk: mediatek: Export PLL operations symbols
  clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier
  clk: mediatek: mt8186-mfg: Propagate rate changes to parent
  clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
  clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
  clk: mediatek: mt8183: Compress top_divs array entries
  clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks

* clk-trace:
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request

* clk-qcom: (69 commits)
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_register
  clk: qcom: rpmh: remove usage of platform name
  clk: qcom: rpmh: rename VRM clock data
  clk: qcom: rpmh: rename ARC clock data
  clk: qcom: rpmh: support separate symbol name for the RPMH clocks
  clk: qcom: rpmh: remove platform names from BCM clocks
  clk: qcom: rpmh: drop all _ao names
  clk: qcom: rpmh: reuse common duplicate clocks
  clk: qcom: rpmh: group clock definitions together
  clk: qcom: rpm: drop the platform from clock definitions
  clk: qcom: rpm: drop the _clk suffix completely
  ...

* clk-microchip:
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: microchip: check for null return of devm_kzalloc()
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek frequency hopping and spread spectrum clocking control

maintainers:
  - Edward-JW Yang <edward-jw.yang@mediatek.com>

description: |
  Frequency hopping control (FHCTL) is a piece of hardware that control
  some PLLs to adopt "hopping" mechanism to adjust their frequency.
  Spread spectrum clocking (SSC) is another function provided by this hardware.

properties:
  compatible:
    const: mediatek,mt8186-fhctl

  reg:
    maxItems: 1

  clocks:
    description: Phandles of the PLL with FHCTL hardware capability.
    minItems: 1
    maxItems: 30

  mediatek,hopping-ssc-percent:
    description: The percentage of spread spectrum clocking for one PLL.
    minItems: 1
    maxItems: 30
    items:
      default: 0
      minimum: 0
      maximum: 8

required:
  - compatible
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8186-clk.h>
    fhctl: fhctl@1000ce00 {
        compatible = "mediatek,mt8186-fhctl";
        reg = <0x1000ce00 0x200>;
        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
        mediatek,hopping-ssc-percent = <3>;
    };
+1 −1
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm A53 PLL Binding
title: Qualcomm A53 PLL clock

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
+1 −1
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm A7 PLL Binding
title: Qualcomm A7 PLL clock

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+7 −4
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
title: LPASS Always ON Clock Controller on SM8250 SoCs

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@@ -17,7 +17,7 @@ description: |

properties:
  compatible:
    const: qcom,sm8250-lpass-aon
    const: qcom,sm8250-lpass-aoncc

  reg:
    maxItems: 1
@@ -28,11 +28,13 @@ properties:
  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio codec voting clock
      - description: Glitch Free Mux register clock

  clock-names:
    items:
      - const: core
      - const: audio
      - const: bus

required:
@@ -50,9 +52,10 @@ examples:
    #include <dt-bindings/sound/qcom,q6afe.h>
    clock-controller@3800000 {
      #clock-cells = <1>;
      compatible = "qcom,sm8250-lpass-aon";
      compatible = "qcom,sm8250-lpass-aoncc";
      reg = <0x03380000 0x40000>;
      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
      clock-names = "core", "bus";
      clock-names = "core", "audio", "bus";
    };
+5 −2
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@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
title: LPASS Audio Clock Controller on SM8250 SoCs

maintainers:
  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
@@ -28,11 +28,13 @@ properties:
  clocks:
    items:
      - description: LPASS Core voting clock
      - description: LPASS Audio codec voting clock
      - description: Glitch Free Mux register clock

  clock-names:
    items:
      - const: core
      - const: audio
      - const: bus

required:
@@ -53,6 +55,7 @@ examples:
      compatible = "qcom,sm8250-lpass-audiocc";
      reg = <0x03300000 0x30000>;
      clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
               <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
      clock-names = "core", "bus";
      clock-names = "core", "audio", "bus";
    };
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