Commit 503fa6d1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'mtk-clk-for-6.2' of... 

Merge tag 'mtk-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux into clk-mediatek

Pull MediaTek clk driver changes from Chen-Yu Tsai:

Some more cleanup work, and a new driver for frequency hopping
controller hardware.

 - Remove flags from univ/main/syspll child fixed factor clocks across
   MediaTek platforms
   - The idea is to not have the clk core try to reconfigure the system
     PLLs, i.e. have them be stable
 - Fix clock dependency for ADC on MT7986
 - New driver for frequency hopping controller hardware on MT8186
   - This does frequency hopping and spread spectrum clocks in hardware

* tag 'mtk-clk-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/wens/linux:
  clk: mediatek: fix dependency of MT7986 ADC clocks
  clk: mediatek: Change PLL register API for MT8186
  clk: mediatek: Add new clock driver to handle FHCTL hardware
  dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
  clk: mediatek: Export PLL operations symbols
  clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier
  clk: mediatek: mt8186-mfg: Propagate rate changes to parent
  clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
  clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
  clk: mediatek: mt8183: Compress top_divs array entries
  clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks
parents 9abf2313 a4631529

Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek frequency hopping and spread spectrum clocking control



maintainers:

  - Edward-JW Yang <edward-jw.yang@mediatek.com>



description: |

  Frequency hopping control (FHCTL) is a piece of hardware that control

  some PLLs to adopt "hopping" mechanism to adjust their frequency.

  Spread spectrum clocking (SSC) is another function provided by this hardware.



properties:

  compatible:

    const: mediatek,mt8186-fhctl



  reg:

    maxItems: 1



  clocks:

    description: Phandles of the PLL with FHCTL hardware capability.

    minItems: 1

    maxItems: 30



  mediatek,hopping-ssc-percent:

    description: The percentage of spread spectrum clocking for one PLL.

    minItems: 1

    maxItems: 30

    items:

      default: 0

      minimum: 0

      maximum: 8



required:

  - compatible

  - reg

  - clocks



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8186-clk.h>

    fhctl: fhctl@1000ce00 {

        compatible = "mediatek,mt8186-fhctl";

        reg = <0x1000ce00 0x200>;

        clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;

        mediatek,hopping-ssc-percent = <3>;

    };

drivers/clk/mediatek/Kconfig

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@@ -11,6 +11,13 @@ config COMMON_CLK_MEDIATEK 
	help

	  MediaTek SoCs' clock support.



config COMMON_CLK_MEDIATEK_FHCTL

	bool "clock driver for MediaTek FHCTL hardware control"

	select COMMON_CLK_MEDIATEK

	help

	  This driver supports MediaTek frequency hopping and

	  spread spectrum clocking features.



config COMMON_CLK_MT2701

	bool "Clock driver for MediaTek MT2701"

	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
@@ -553,6 +560,7 @@ config COMMON_CLK_MT8186 
	bool "Clock driver for MediaTek MT8186"

	depends on ARM64 || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	select COMMON_CLK_MEDIATEK_FHCTL

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT8186 clocks.

drivers/clk/mediatek/Makefile

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# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o

obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o



obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o

obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o

drivers/clk/mediatek/clk-fhctl.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>

 */



#include <linux/io.h>

#include <linux/iopoll.h>



#include "clk-mtk.h"

#include "clk-pllfh.h"

#include "clk-fhctl.h"



#define PERCENT_TO_DDSLMT(dds, percent_m10) \

	((((dds) * (percent_m10)) >> 5) / 100)



static const struct fhctl_offset fhctl_offset = {

	.offset_hp_en = 0x0,

	.offset_clk_con = 0x8,

	.offset_rst_con = 0xc,

	.offset_slope0 = 0x10,

	.offset_slope1 = 0x14,

	.offset_cfg = 0x0,

	.offset_updnlmt = 0x4,

	.offset_dds = 0x8,

	.offset_dvfs = 0xc,

	.offset_mon = 0x10,

};



const struct fhctl_offset *fhctl_get_offset_table(void)

{

	return &fhctl_offset;

}



static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,

		    const struct fh_pll_data *data)

{

	pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",

		readl(regs->reg_hp_en), readl(regs->reg_clk_con),

		readl(regs->reg_slope0), readl(regs->reg_slope1));

	pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",

		readl(regs->reg_cfg), readl(regs->reg_updnlmt),

		readl(regs->reg_dds), readl(regs->reg_dvfs),

		readl(regs->reg_mon));

	pr_info("pcw<%x>\n", readl(pll->pcw_addr));

}



static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,

			      const struct fh_pll_data *data, u32 rate)

{

	u32 updnlmt_val, r;



	writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);

	writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);

	writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);



	if (rate > 0) {

		/* Set the relative parameter registers (dt/df/upbnd/downbnd) */

		r = readl(regs->reg_cfg);

		r &= ~(data->msk_frddsx_dys);

		r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));

		writel(r, regs->reg_cfg);



		r = readl(regs->reg_cfg);

		r &= ~(data->msk_frddsx_dts);

		r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));

		writel(r, regs->reg_cfg);



		writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,

			regs->reg_dds);



		/* Calculate UPDNLMT */

		updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &

						 data->dds_mask), rate) <<

						 data->updnlmt_shft;



		writel(updnlmt_val, regs->reg_updnlmt);

		writel(readl(regs->reg_hp_en) | BIT(data->fh_id),

		       regs->reg_hp_en);

		/* Enable SSC */

		writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);

		/* Enable Hopping control */

		writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);



	} else {

		/* Switch to APMIXEDSYS control */

		writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),

		       regs->reg_hp_en);

		/* Wait for DDS to be stable */

		udelay(30);

	}



	return 0;

}



static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,

			   const struct fh_pll_data *data,

			   struct fh_pll_state *state, unsigned int new_dds)

{

	u32 dds_mask = data->dds_mask;

	u32 mon_dds = 0;

	u32 con_pcw_tmp;

	int ret;



	if (state->ssc_rate)

		fhctl_set_ssc_regs(pll, regs, data, 0);



	writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,

		regs->reg_dds);



	writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);

	writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);

	writel(data->slope0_value, regs->reg_slope0);

	writel(data->slope1_value, regs->reg_slope1);



	writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);

	writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);



	/* Wait 1000 us until DDS stable */

	ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,

				       (mon_dds & dds_mask) == new_dds,

					10, 1000);

	if (ret) {

		pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);

		dump_hw(pll, regs, data);

	}



	con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);

	con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |

		       data->pcwchg);



	writel(con_pcw_tmp, pll->pcw_addr);

	writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);



	if (state->ssc_rate)

		fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);



	return ret;

}



static unsigned int __get_postdiv(struct mtk_clk_pll *pll)

{

	unsigned int regval;



	regval = readl(pll->pd_addr) >> pll->data->pd_shift;

	regval &= POSTDIV_MASK;



	return BIT(regval);

}



static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)

{

	unsigned int regval;



	regval = readl(pll->pd_addr);

	regval &= ~(POSTDIV_MASK << pll->data->pd_shift);

	regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;

	writel(regval, pll->pd_addr);

}



static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,

			 unsigned int postdiv)

{

	const struct fh_pll_data *data = &fh->pllfh_data->data;

	struct fh_pll_state *state = &fh->pllfh_data->state;

	struct fh_pll_regs *regs = &fh->regs;

	struct mtk_clk_pll *pll = &fh->clk_pll;

	spinlock_t *lock = fh->lock;

	unsigned int pll_postdiv;

	unsigned long flags = 0;

	int ret;



	if (postdiv) {

		pll_postdiv = __get_postdiv(pll);



		if (postdiv > pll_postdiv)

			__set_postdiv(pll, postdiv);

	}



	spin_lock_irqsave(lock, flags);



	ret = hopping_hw_flow(pll, regs, data, state, new_dds);



	spin_unlock_irqrestore(lock, flags);



	if (postdiv && postdiv < pll_postdiv)

		__set_postdiv(pll, postdiv);



	return ret;

}



static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)

{

	const struct fh_pll_data *data = &fh->pllfh_data->data;

	struct fh_pll_state *state = &fh->pllfh_data->state;

	struct fh_pll_regs *regs = &fh->regs;

	struct mtk_clk_pll *pll = &fh->clk_pll;

	spinlock_t *lock = fh->lock;

	unsigned long flags = 0;



	spin_lock_irqsave(lock, flags);



	fhctl_set_ssc_regs(pll, regs, data, rate);

	state->ssc_rate = rate;



	spin_unlock_irqrestore(lock, flags);



	return 0;

}



static const struct fh_operation fhctl_ops = {

	.hopping = fhctl_hopping,

	.ssc_enable = fhctl_ssc_enable,

};



const struct fh_operation *fhctl_get_ops(void)

{

	return &fhctl_ops;

}



void fhctl_hw_init(struct mtk_fh *fh)

{

	const struct fh_pll_data data = fh->pllfh_data->data;

	struct fh_pll_state state = fh->pllfh_data->state;

	struct fh_pll_regs regs = fh->regs;

	u32 val;



	/* initial hw register */

	val = readl(regs.reg_clk_con) | BIT(data.fh_id);

	writel(val, regs.reg_clk_con);



	val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);

	writel(val, regs.reg_rst_con);

	val = readl(regs.reg_rst_con) | BIT(data.fh_id);

	writel(val, regs.reg_rst_con);



	writel(0x0, regs.reg_cfg);

	writel(0x0, regs.reg_updnlmt);

	writel(0x0, regs.reg_dds);



	/* enable ssc if needed */

	if (state.ssc_rate)

		fh->ops->ssc_enable(fh, state.ssc_rate);

}

drivers/clk/mediatek/clk-fhctl.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2022 MediaTek Inc.

 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>

 */



#ifndef __CLK_FHCTL_H

#define __CLK_FHCTL_H



struct fhctl_offset {

	u32 offset_hp_en;

	u32 offset_clk_con;

	u32 offset_rst_con;

	u32 offset_slope0;

	u32 offset_slope1;

	u32 offset_cfg;

	u32 offset_updnlmt;

	u32 offset_dds;

	u32 offset_dvfs;

	u32 offset_mon;

};

const struct fhctl_offset *fhctl_get_offset_table(void);

const struct fh_operation *fhctl_get_ops(void);

void fhctl_hw_init(struct mtk_fh *fh);



#endif